ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 63

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

Bit
5
4
3
2
1
0
I
Name:
Address:
Default value:
Access:
Function:
2
C Slave Status Registers, I2CxSSTA
Name
I2CSETEN
I2CGCCLR
I2CHGCEN
I2CGCEN
ADR10EN
I2CSEN
I2C0SSTA, I2C1SSTA
0xFFFF082C, 0xFFFF092C
0x0000, 0x0000
Read/write
These 16-bit MMRs are the I
Description
I
This bit is set to enable a transmit request interrupt just after the positive edge of SCL during the read bit
transmission.
This bit is cleared to enable a transmit request interrupt just after the negative edge of SCL during the read bit
transmission.
I
Writing a 1 to this bit clears the general call status and ID bits in the I2CxSSTA register.
This bit is cleared at all other times.
I
received a general call (Address 0x00) and a data byte, the device checks the contents of the I2CxALT against
the receive register. If the contents match, the device has received a hardware general call. This is used if a
device needs urgent attention from a master device without knowing which master it needs to turn to. This is a
broadcast message to all master devices on the bus. The ADuC7023 watches for these addresses. The device
that requires attention embeds its own address into the message. All masters listen, and the one that can
handle the device contacts its slave and acts appropriately. The LSB of the I2CxALT register should always be
written to 1, as per the I
This bit and I2CGCEN are set to enable hardware general call recognition in slave mode.
This bit is cleared to disable recognition of hardware general call commands.
I
0x00 (write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of
the slave address by hardware) as the data byte, the I
specification. This command can be used to reset an entire I
programmable part of the slave address by hardware) as the data byte, the general call interrupt status bit sets
on any general call. The user must take corrective action by reprogramming the device address.
This bit is set to allow the slave acknowledge I
This bit is cleared to disable recognition of general call commands.
I
This bit is set to 1 to enable 10-bit address mode.
This bit is cleared to 0 to enable normal address mode.
I
This bit is set by user to enable I
This bit is cleared by the user to disable I
2
2
2
2
2
2
C early transmit interrupt enable bit.
C general call status and ID clear bit.
C hardware general call enable. Hardware general call enable. When this bit and Bit 2 are set, and having
C general call enable. This bit is set to enable the slave device to acknowledge an I
C 10-bit address mode.
C slave enable bit.
2
C status registers in slave mode.
2
C January 2000 bus specification.
2
Rev. B | Page 63 of 96
C slave mode.
2
C slave mode.
2
C general call commands.
2
C interface resets as per the I
2
C system. If it receives a 0x04 (write
2
C January 2000 bus
2
C general call, Address
ADuC7023