ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 64

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

ADuC7023
Table 72. I2CxSSTA MMR Bit Designations
Bit
15
14
13
12 to 11
10
9 to 8
7
6
5
4
3
2
Name
I2CSTA
I2CREPS
I2CID[1:0]
I2CSS
I2CGCID[1:0]
I2CGC
I2CSBUSY
I2CSNA
I2CSRxFO
I2CSRXQ
I2CSTXQ
Description
Reserved bit.
This bit is set to 1 if: A start condition followed by a matching address is detected. It is also set if a start
byte (0x01) is received. If general calls are enabled and a general call code of (0x00) is received.
This bit is cleared on receiving a stop condition.
This bit is set to 1 if a repeated start condition is detected.
This bit is cleared on receiving a stop condition.
I
[00] = received address matches I2CxID0.
[01] = received address matches I2CxID1.
[10] = received address matches I2CxID2.
[11] = received address matches I2CxID3.
I
This bit is set to 1 when a stop condition is detected after a previous start and matching address.
When the I2CSSENI bit in I2CxSCON is set, an interrupt is generated.
This bit is cleared by reading this register.
I
[00] = no general call received.
[01] = general call reset and program address.
[10] = general program address.
[11] = general call matching alternative ID.
These bits are not cleared by a general call reset command.
These bits are cleared by writing a 1 to the I2CGCCLR bit in I2CxSCON.
I
This bit is set to 1 if the slave receives a general call command of any type. If the command received is a
reset command, then all registers return to their default state. If the command received is a hardware
general call, the Rx FIFO holds the second byte of the command, and this can be compared with the
I2CxALT register.
This bit is cleared by writing a 1 to the I2CGCCLR bit in I2CxSCON.
I
This bit is set to 1 when the slave receives a start condition.
This bit is cleared by hardware if the received address does not match any of the I2CxIDx registers, the
slave device receives a stop condition or if a repeated start address does not match any of the I2CxIDx
registers.
I
This bit is set to 1 when the slave responds to a bus address with a no acknowledge. This bit is asserted
under the following conditions: if no acknowledge is returned because there is no data in the Tx FIFO or if
the I2CNACKEN bit is set in the I2CxSCON register.
This bit is cleared in all other conditions.
Slave Rx FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
I
This bit is set to 1 when the slave Rx FIFO is not empty. This bit causes an interrupt to occur if the
I2CSRXENI bit in I2CxSCON is set.
The Rx FIFO must be read or flushed to clear this bit.
I
This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in
I2CxSCON is = 0, , this bit goes high just after the negative edge of SCL during the read bit transmission. If
the I2CSETEN bit in I2CxSCON is = 1, this bit goes high just after the positive edge of SCL during the read
bit transmission. This bit causes an interrupt to occur if the I2CSTXENI bit in I2CxSCON is set.
This bit is cleared in all other conditions.
2
2
2
2
2
2
2
2
C address matching register. These bits indicate which I2CxIDx register matches the received address.
C stop condition after start detected bit.
C general call ID bits.
C general call status bit.
C slave busy status bit.
C slave no acknowledge data bit.
C slave receive request bit.
C slave transmit request bit.
Rev. B | Page 64 of 96