ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 67

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

PLA MMRs Interface
The PLA peripheral interface consists of the 22 MMRs described in the following sections.
PLAELMx Registers
PLAELMx are Element 0 to Element 15 control registers. They configure the input and output mux of each element, select the function in
the look-up table, and bypass/use the flip-flop (see Table 76).
Table 75. PLAELMx Registers
Name
PLAELM0
PLAELM1
PLAELM2
PLAELM3
PLAELM4
PLAELM5
PLAELM6
PLAELM7
PLAELM8
PLAELM9
PLAELM10
PLAELM11
PLAELM12
PLAELM13
PLAELM14
PLAELM15
Table 76. PLAELMx MMR Bit Descriptions
Bit
31 to 11
10 to 9
8 to 7
6
5
4 to 1
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Address
0xFFFF0B00
0xFFFF0B04
0xFFFF0B08
0xFFFF0B0C
0xFFFF0B10
0xFFFF0B14
0xFFFF0B18
0xFFFF0B1C
0xFFFF0B20
0xFFFF0B24
0xFFFF0B28
0xFFFF0B2C
0xFFFF0B30
0xFFFF0B34
0xFFFF0B38
0xFFFF0B3C
Description
Reserved.
Mux 0 control (see Table 80).
Mux 1 control (see Table 80).
Mux 2 control.
This bit is set by the user to select the output of Mux 0.
This bit is cleared by the user to select the bit value from the PLADIN register.
Mux 3 control.
This bit is set by the user to select the input pin of the particular element.
This bit is cleared by the user to select the output of Mux 1.
Look-up table control.
0.
NOR.
B and not A.
Not A.
A and not B.
Not B.
EXOR.
NAND.
AND.
EXNOR.
B.
Not A or B.
A.
A or not B.
OR.
1.
Rev. B | Page 67 of 96
Default Value
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADuC7023