ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 83

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

T0CON Register
Name:
Address:
Default value:
Access:
T0CON is the configuration MMR described in Table 100.
Table 100. T0CON MMR Bit Descriptions
Bit
15 to 8
7
6
5 to 4
3 to 2
1 to 0
T0CLRI Register
Name:
Address:
Default value:
Access:
T0CLRI is an 8-bit register. Writing any value to this register
clears the interrupt.
Timer1 (General-Purpose Timer)
Timer1 is a general-purpose, 32-bit timer (count down or count
up) with a programmable prescaler. The source can be the
32 kHz external crystal, the undivided system, the core clock, or
P1.1 (maximum frequency 44 MHz). This source can be scaled
by a factor of 1, 16, 256, or 32,768.
The counter can be formatted as a standard 32-bit value or as
hours, minutes, seconds, hundredths.
Timer1 has a capture register (T1CAP) that can be triggered by
a selected IRQ source initial assertion. This feature can be used
to determine the assertion of an event more accurately than the
precision allowed by the RTOS timer when the IRQ is serviced.
Value
00
01
10
11
00
01
10
11
T0CON
0xFFFF0308
0x0000
R/W
Description
Reserved.
Timer0 enable bit.
This bit is set by the user to enable Timer0. This
bit is cleared by the user to disable Timer0 by
default.
Timer0 mode.
This bit is set by the user to operate in
periodic mode.
This bit is cleared by the user to operate in
free-running mode. Default mode.
Clock select bits.
HCLK.
UCLK.
Internal 32768 Hz oscillator.
Reserved.
Source clock/1. Default value.
Source clock/16.
Source clock/256.
Undefined. Equivalent to 00.
Reserved.
T0CLRI
0xFFFF030C
0xXX
Write
Rev. B | Page 83 of 96
Timer1 can be used to start ADC conversions as shown in the
block diagram in Figure 43.
32kHz OSCILLATOR
The Timer1 interface consists of five MMRs: T1LD, T1VAL,
T1CON, T1CLRI, and T1CAP.
T1LD Register
Name:
Address:
Default value:
Access:
T1LD is a 32-bit load register.
T1VAL Register
Name:
Address:
Default value:
Access:
T1VAL is a 32-bit read-only register that represents the current
state of the counter.
T1CON Register
Name:
Address:
Default value:
Access:
T1CON is the configuration MMR described in Table 101.
HCLK
UCLK
P1.1
Figure 43. Timer1 Block Diagram
T1LD
0xFFFF0320
0x00000000
Read/write
T1VAL
0xFFFF0324
0xFFFFFFFF
Read
T1CON
0xFFFF0328
0x00000000
Read/write
IRQ[19:0]
PRESCALER
/1, 16, 256,
OR 32,768
UP/DOWN
COUNTER
CAPTURE
32-BIT
32-BIT
LOAD
TIMER1
VALUE
ADuC7023
TIMER1 IRQ
ADC CONVERSION