ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 85

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

T2LD Register
Name:
Address:
Default
value:
Access:
T2LD is a 16-bit register load register.
T2VAL Register
Name:
Address:
Default
value:
Access:
T2VAL is a 16-bit read-only register that represents the current
state of the counter.
T2CON Register
Name:
Address:
Default
value:
Access:
T2CON is the configuration MMR described in Table 102.
Table 102. T2CON MMR Bit Descriptions
Bit
15 to 9
8
7
Value
T2LD
0xFFFF0360
0x0000
Read/write
T2VAL
0xFFFF0364
0xFFFF
Read
T2CON
0xFFFF0368
0x0000
Read/write
Description
Reserved.
Count up.
This bit is set by the user for Timer2 to
count up.
This bit is cleared by the user for Timer2 to
count down by default.
Timer2 enable bit.
This bit is set by the user to enable Timer2.
This bit is cleared by user to disable Timer2
by default.
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Bit
6
5
4
3 to 2
1
0
T2CLRI Register
Name:
Address:
Default value:
Access:
T2CLRI is an 8-bit register. Writing any value to this register on
successive occassions clears the Timer2 interrupt in normal
mode or resets a new timeout period in watchdog mode .
The user must perform successive writes to this register to
ensure resetting the timeout period.
Value
00
01
10
11
T2CLRI
0xFFFF036C
0xXX
Write
Description
Timer2 mode.
This bit is set by user to operate in periodic
mode.
This bit is cleared by the user to operate in
free-running mode. Default mode.
Watchdog mode enable bit.
This bit is set by the user to enable
watchdog mode.
This bit is cleared by the user to disable
watchdog mode by default.
Secure clear bit.
This bit is set by the user to use the secure
clear option.
This bit is cleared by the user to disable the
secure clear option by default.
Prescale.
Source clock/1 by default.
Source clock/16.
Source clock/256.
Undefined. Equivalent to 00.
Watchdog IRQ Option Bit.
This bit is set by the user to produce an IRQ
instead of a reset when the watchdog
reaches 0.
This bit is cleared by the user to disable the
IRQ option.
Reserved.
ADuC7023