ADUC7029 Analog Devices, ADUC7029 Datasheet - Page 66

• Manufacturer Part Number: ADUC7029
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7029

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8152Bytes
• Gpio Pins: 22
• Adc # Channels: 7

ADuC7019/20/21/22/24/25/26/27/28/29
The serial communication adopts an asynchronous protocol,
which supports various word lengths, stop bits, and parity
generation options selectable in the configuration register.
Baud Rate Generation
There are two ways of generating the UART baud rate, normal
450 UART baud rate generation and the fractional divider.
Normal 450 UART Baud Rate Generation
The baud rate is a divided version of the core clock using the values
in the COMDIV0 and COMDIV1 MMRs (16-bit value, DL).
Table 91 gives some common baud rate values.
Table 91. Baud Rate Using the Normal Baud Rate Generator
Baud Rate
9600
19,200
115,200
9600
19,200
115,200
Fractional Divider
The fractional divider, combined with the normal baud rate
generator, produces a wider range of more accurate baud rates.
Calculation of the baud rate using fractional divider is as follows:
For example, generation of 19,200 baud with CD bits = 3
(Table 91 gives DL = 0x08) is
where:
M = 1
N = 0.06 × 2048 = 128
Baud
Baud
M
M
M
Baud
+
+
+
CLOCK
CORE
2048
2048
2048
Rate
Rate
Rate
N
N
N
Figure 63. Baud Rate Generation Options
CD
0
0
0
3
3
3
=
=
=
/(M+N/2048)
=
=
=
. 1
19200
Baud
2
2
2
06
3
CD
/2
CD
×
41
DL
0x88
0x44
0x0B
0x11
0x08
0x01
×
16
41
×
.
Rate
41
78
16
16
×
×
.
78
2
.
8
MHz
×
×
78
3
41
×
41
MHz
FBEN
DL
×
2
×
2
MHz
.
16
×
Actual Baud Rate
9600
19,200
118,691
9600
20,400
163,200
78
.
×
78
2
×
DL
×
CD
⎛
⎜
⎝
MHz
2
MHz
8
2048
×
128
×
×
⎛
⎜
⎝
2
16
/16DL
M
⎞
⎟
⎠
+
×
DL
2048
N
×
2
⎞
⎟
⎠
UART
% Error
0
0
3
0
6.25
41.67
Rev. D | Page 66 of 96
where:
Baud Rate = 19,200 bps
Error = 0%, compared to 6.25% with the normal baud rate
generator.
UART Register Definitions
The UART interface consists of 12 registers: COMTX, COMRX,
COMDIV0, COMIEN0, COMDIV1, COMIID0, COMCON0,
COMCON1, COMSTA0, COMSTA1, COMSCR, and
COMDIV2.
Table 92. COMTX Register
Name
COMTX
COMTX is an 8-bit transmit register.
Table 93. COMRX Register
Name
COMRX
COMRX is an 8-bit receive register.
Table 94. COMDIV0 Register
Name
COMDIV0
COMDIV0 is a low byte divisor latch. COMTX, COMRX,
and COMDIV0 share the same address location. COMTX
and COMRX can be accessed when Bit 7 in the COMCON0
register is cleared. COMDIV0 can be accessed when Bit 7
of COMCON0 is set.
Table 95. COMIEN0 Register
Name
COMIEN0
COMIEN0 is the interrupt enable register.
Table 96. COMIEN0 MMR Bit Descriptions
Bit
7:4
3
2
1
0
Table 97. COMDIV1 Register
Name
COMDIV1
COMDIV1 is a divisor latch (high byte) register.
Name
N/A
EDSSI
ELSI
ETBEI
ERBFI
Address
0xFFFF0700
Address
0xFFFF0700
Address
0xFFFF0700
Address
0xFFFF0704
Address
0xFFFF0704
Description
Reserved.
Modem status interrupt enable bit. Set by
user to enable generation of an interrupt if
any of COMSTA1[3:1] is set. Cleared by user.
Rx status interrupt enable bit. Set by user to
enable generation of an interrupt if any of
COMSTA0[3:0] is set. Cleared by user.
Enable transmit buffer empty interrupt. Set
by user to enable interrupt when buffer is
empty during a transmission. Cleared by user.
Enable receive buffer full interrupt. Set by
user to enable interrupt when buffer is full
during a reception. Cleared by user.
Default Value
0x00
Default Value
0x00
Default Value
0x00
Default Value
0x00
Default Value
0x00
Access
R/W
Access
R
Access
R/W
Access
R/W
Access
R/W