ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 31

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

Table 30. ADCCP
Bit
7:5
4:0
1
Table 31. ADCCN
Bit
7:5
4:0
1
ADC channel availability depends on part model.
ADC channel availability depends on part model.
Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
Others
Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
Others
Description
Reserved
Positive channel selection bits
PADC0P
PADC1P
Reserved
Reserved
Reserved
Reserved
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10/AINCM
Temperature sensor
DVDD_IDAC0
DVDD_IDAC1
DVDD_IDAC2
DVDD_IDAC3
DVDD_IDAC4
IOVDD_MON
Reserved
Reserved
V
AGND
Reserved
1
REF
1
MMR Bit Designations
Description
Reserved
Negative channel selection bits
PADC0N
PADC1N
Reserved
Reserved
Reserved
Reserved
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10/AINCM
V
AGND
PGND
IOGND
Reserved
MMR Bit Designations
REF
Rev. 0 | Page 31 of 96
Table 32. ADCSTA MMR Bit Designations
Bit
0
0
Table 33. ADCDAT MMR Bit Designations
Bit
27:16
Table 34. ADCRST MMR Bit Designations
Bit
0
Table 35. PGA_GN MMR Bit Designations
Bit
11:6
5:0
1
2
Table 36. ADCGN MMR Bit Designations
Bit
11:6
9:0
1
Table 37. ADCOF MMR Bit Designations
Bit
15:10
9:0
1
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge sampled input stage. This
architecture is described for the three different modes of
operation: differential, pseudo differential, and single-ended.
Differential Mode
The ADuC7121 contains a successive approximation ADC
based on two capacitive DACs. Figure 18 and Figure 19 show
simplified schematics of the ADC in acquisition and conversion
phase, respectively. The ADC comprises control logic, a SAR, and
two capacitive DACs. In Figure 18 (the acquisition phase), SW3
is closed and SW1 and SW2 are in Position A. The comparator
is held in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
PGA_PADC0_GN and PGA_PADC1_GN must be ≤ 32.
N/A means not applicable.
N/A means not applicable.
N/A means not applicable.
Value
N/A
N/A
Value
N/A
N/A
Value
1
0
Value
Value
1
Value
N/A
N/A
2
1
1
Description
Gain of PGA for PADC0 = 1 + 4 ×
(PGA_PADC0_GN/32).
Gain of PGA for PADC1 = 1 + 4 ×
(PGA_PADC1_GN/32).
Description
These bits are reserved.
10-bit ADC gain calibration value for non-PGA
channels.
Description
These bits are reserved.
10-bit ADC offset calibration value.
Description
Holds the ADC result (see Figure 15).
Description
Set to 1 by the user to reset all the ADC
registers to their default values.
Description
Indicates that an ADC conversion is complete. It
is set automatically after an ADC conversion
completes.
Automatically cleared by reading the
ADCDAT MMR.
1
ADuC7121