ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 43

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

Using the DACs
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier. The functional equivalent
is shown in Figure 29.
As shown in Figure 29, the reference source for each DAC is user-
selectable in software. It can be either AV
0 V-to-AV
0 V to the voltage at the AVDD pin. In 0 V-to-EXT_REF mode,
the DAC output transfer function spans from 0 V to the voltage at
the V
function spans from 0 V to the internal 2.5 V reference, V
The DAC output buffer amplifier features a true rail-to-rail
output stage implementation. This means that, when unloaded,
each output is capable of swinging to within less than 5 mV of
both AV
DAC (when driving a 5 kΩ resistive load to ground) is guaranteed
through the full transfer function except for Code 0 to Code 100,
and, in 0 V-to-AV
Linearity degradation near ground and AV
ration of the output amplifier, and a general representation of its
effects (neglecting offset and gain error) is shown in Figure 30. The
dotted line in Figure 30 indicates the ideal transfer function, and
the solid line represents what the transfer function may look
like with endpoint nonlinearities due to saturation of the output
amplifier. Note that Figure 30 represents a transfer function in 0 V-
to-AV
(with V
is similar. However, the upper portion of the transfer function
follows the ideal line right to the end (V
showing no signs of endpoint linearity errors.
REF
DD
_2.5 pin. In 0 V-to-V
REF
DD
mode only. In 0 V-to-V
EXT_REF
DD
and ground. Moreover, the linearity specification of the
< AV
mode, the DAC output transfer function spans from
AV
V
REF
DD
DD
DD
or EXT_REF < AV
mode only, Code 3995 to Code 4095.
Figure 29. DAC Structure
R
R
R
R
R
REF
mode, the DAC output transfer
REF
or 0 V-to-EXT_REF modes
DD
REF
), the lower nonlinearity
DD
in this case, not AV
, V
DD
REF
is caused by satu-
, or EXT_REF. In
DAC0
REF
.
DD
Rev. 0 | Page 43 of 96
),
The endpoint nonlinearities conceptually illustrated in Figure 30
worsen as a function of output loading. The ADuC7121 data sheet
specifications assume a 5 kΩ resistive load to ground at the DAC
output. As the output is forced to source or sink more current,
the nonlinear regions at the top or bottom (respectively) of
Figure 30 become larger. With larger current demands, this can
significantly limit output voltage swing.
LDO (LOW DROPOUT REGULATOR)
The ADuC7121 contains an integrated LDO, which generates
the core supply voltage (DVDD) of approximately 2.6 V from
the IOVDD supply. As the LDO is driven from IOVDD, the
IOVDD supply voltage needs to be greater than 2.7 V.
An external compensation capacitor (CT) of 0.47 μF with low
ESR must be placed very close to each of the DVDD pins. This
capacitor also acts as a storage tank of charge, and supplies an
instantaneous charge required by the core, particularly at the
positive edge of the core clock (HCLK).
The DVDD voltage generated by the LDO is solely for providing
a supply for the ADuC7121. Therefore, users should not use a
DVDD pin as the power supply pin for any other chip. In
addition, it is recommended that the IOVDD has excellent
power supply decoupling to help improve line regulation
performance of the LDO.
The DVDD pin has no reverse battery, current limit, or thermal
shutdown protection; therefore, it is essential that users of the
ADuC7121 do not short this pin to ground at any time during
normal operation or during board manufacture.
CURRENT OUTPUT DACs (IDAC)
The ADuC7121 provides five current output digital-to-analog
converters (DACs). The current sources (five current DACs)
feature low noise and low drift high-side current output with
11-bit resolution. The five IDACs are as follows: IDAC0 with
250 mA full-scale (FS) output, IDAC1 with 200 mA FS output,
IDAC2 with 80 mA FS output, IDAC3 with 45 mA FS output,
and IDAC4 with 20 mA FS output.
Figure 30. Endpoint Nonlinearities Due to Amplifier Saturation
AV
DD
– 100mV
100mV
AV
DD
0x00000000
0x0FFF0000
ADuC7121