ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 63

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

I
The ADuC7121 incorporates two I
configured as a fully I
fully I
identical.
The two pins used for data transfer, SDA and SCL, are configured
in a wired-AND format that allows arbitration in a multimaster
system. These pins require external pull-up resistors. Typical
pull-up values are between 4.7 kΩ and 10 kΩ.
The address of the I
programmed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
The transfer sequence of an I
initiating a transfer by generating a start condition while the bus
is idle. The master transmits the slave device address and the
direction of the data transfer (R/ W ) during the initial address
transfer. If the master does not lose arbitration and the slave
acknowledges, the data transfer is initiated. This continues until
the master issues a stop condition and the bus becomes idle.
The I
at any given time. The same I
support master and slave modes. The I
ADuC7121 includes the following features:
•
•
•
•
•
•
•
•
Configuring External Pins for I
The I
I
signals, and P0.1 and P1.1 are the I
to configure the I
GP0CON register must be set to 1 to enable I
configure the I
2
2
C0, and P1.0 and P1.1 for I
C PERIPHERALS
Support for repeated start conditions. In master mode, the
ADuC7121 can be programmed to generate a repeated
start. In slave mode, the ADuC7121 recognizes repeated
start conditions.
In master and slave modes, the device recognizes both
7-bit and 10-bit bus addresses.
In I
reads from a single slave up to 512 bytes in a single transfer
sequence.
Clock stretching is supported in both master and slave
modes.
In slave mode, the ADuC7121 can be programmed to
return a no acknowledge. This allows the validation of
checksum bytes at the end of I
Bus arbitration in master mode is supported.
Internal and external loopback modes are supported for
I
The transmit and receive circuits in both master and slave
mode contain 2-byte FIFOs. Status bits are available to the
user to control these FIFOs.
2
2
2
2
C peripheral can only be configured as a master or slave
C pins of the ADuC7121 device are P0.0 and P0.1 for
C hardware testing in loopback mode.
C-compatible bus slave device. Both peripherals are
2
C Master mode, the ADuC7121 supports continuous
2
C1 pins (SCL1, SDA1), Bit 1 and Bit 5 of the
2
C0 pins (SCL0, SDA0), Bit 0 and Bit 4 of the
2
C bus peripheral in the I
2
C-compatible bus master device or as a
2
2
2
C1. P0.0 and P1.0 are the I
C system consists of a master device
C channel cannot simultaneously
2
2
C Functionality
2
2
C data signals. For instance,
C peripherals that may be
C transfers.
2
C interface on the
2
2
C bus system is
C mode. To
2
C clock
Rev. 0 | Page 63 of 96
GP1CON register must be set to 1 to enable I
in the
General-Purpose Input/Output section.
SERIAL CLOCK GENERATION
The I
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz). The bit rate
is defined in the I2CDIV MMR as follows:
where:
f
DIVH = the high period of the clock.
DIVL = the low period of the clock.
Thus, for 100 kHz operation
and for 400 kHz
The I2CDIV register corresponds to DIVH:DIVL.
I
Slave Mode
In slave mode, the registers I2CxID0, I2CxID1, I2CxID2, and
I2CxID3 contain the device IDs. The device compares the four
I2CxIDx registers to the address byte received from the bus
master. To be correctly addressed, the 7 MSBs of either ID
register must be identical to that of the 7 MSBs of the first
received address byte. The LSB of the ID registers (the transfer
direction bit) is ignored in the process of address recognition.
The ADuC7121 also supports 10-bit addressing mode. When
Bit 1 of I2CxSCON (ADR10EN bit) is set to 1, then one 10-bit
address is supported in slave mode and is stored in registers
I2CxID0 and I2CxID1. The 10-bit address is derived as follows:
I2CxID0[0] is the read/ write bit and is not part of the I
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Master Mode
In master mode, the I2CxADR0 register is programmed with
the I
In 7-bit address mode, I2CxADR0[7:1] are set to the device
address. I2CxADR0[0] is the read/ write bit.
In 10-bit address mode, the 10-bit address is created as follows:
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•
UCLK
2
C BUS ADDRESSES
2
DIVH = DIVL = 0xCF
DIVH = 0x28, DIVL = 0x3C
I2CxID0[7:1] = Address Bits[6:0].
I2CxID1[2:0] = Address Bits[9:7].
I2CxID1[7:3] must be set to 11110b.
I2CxADR0[7:3] must be set to 11110b.
I2CxADR0[2:1] = Address Bits[9:8].
I2CxADR1[7:0] = Address Bits[7:0].
= clock before the clock divider.
C address of the device.
2
f
C master in the system generates the serial clock for a
SERIAL
CLOCK
=
2 (
+
DIVH
f
UCLK
)
+
(2
+
DIVL
)
2
C mode, as shown
ADuC7121
2
C address.