ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 70

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ADUC7121

Manufacturer Part Number
ADUC7121
Description
Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7121

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Sram (bytes)
8192Bytes
Gpio Pins
32
Adc # Channels
9

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ADuC7121
Bit
4
3
2
1
0
Name
I2CSRxFO
I2CSRXQ
I2CSTXQ
I2CSTFE
I2CETSTA
Description
Slave Rx FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
I
I
I
I
If the I2CSETEN bit in I2CxSCTL is = 0, this bit goes high if the slave Tx FIFO is empty.
If the I2CSETEN bit in I2CxSCTL is = 1, this bit goes high just after the positive edge of SCL during the write bit
transmission. This bit asserts once only for a transfer.
This bit is cleared after being read.
This bit is set to 1 when the Rx FIFO of the slave is not empty. This bit causes an interrupt to occur if the I2CSRXENI
bit in I2CxSCTL is set.
The Rx FIFO must be read or flushed to clear this bit.
This bit is set to 1 when the slave receives a matching address followed by a read.
If the I2CSETEN bit in I2CxSCTL is = 0, this bit goes high just after the negative edge of SCL during the read bit
transmission.
If the I2CSETEN bit in I2CxSCTL is = 1, this bit goes high just after the positive edge of SCL during the read bit
transmission. This bit causes an interrupt to occur if the I2CSTXENI bit in I2CxSCTL is set.
This bit is cleared in all other conditions.
This bit is high if the Tx FIFO is empty when a master requests data from the slave. This bit asserts at the rising edge
of SCL during the read bit.
This bit clears in all other conditions.
2
2
2
2
C slave receive request bit.
C slave transmit request bit.
C slave FIFO underflow status bit.
C slave early transmit FIFO status bit.
Rev. 0 | Page 70 of 96

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