ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 74

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

ADuC7121
Table 97. SPISTA MMR Bit Designations
Bit
15:12
11
10:8
7
6
5
4
3:1
0
SPIRX Register
This 8-bit MMR is the SPI receive register.
Name:
Address:
Default value:
Access:
SPITX Register
This 8-bit MMR is the SPI transmit register.
Name:
Address:
Default value:
Access:
Name
SPIREX
SPIRXFSTA[2:0]
SPIFOF
SPIRXIRQ
SPITXIRQ
SPITXUF
SPITXFSTA[2:0]
SPIISTA
SPIRX
0xFFFF0A04
0x00
Read only
SPITX
0xFFFF0A08
0x00
Write only
Description
Reserved bits.
SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the
SPIMDE bits in SPICON.
This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIMDE.
SPI Rx FIFO status bits.
[000] = Rx FIFO is empty.
[001] = one valid byte in the FIFO.
[010] = two valid bytes in the FIFO.
[011] = three valid bytes in the FIFO.
[100] = four valid bytes in the FIFO.
SPI Rx FIFO overflow status bit.
Set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt
except when SPIRFLH is set in SPICON.
Cleared when the SPISTA register is read.
SPI Rx IRQ status bit.
Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required
number of bytes have been received.
Cleared when the SPISTA register is read.
SPI Tx IRQ status bit.
Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number
of bytes have been transmitted.
Cleared when the SPISTA register is read.
SPI Tx FIFO underflow.
This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt
except when SPITFLH is set in SPICON.
Cleared when the SPISTA register is read.
SPI Tx FIFO status bits.
[000] = Tx FIFO is empty.
[001] = one valid byte in the FIFO.
[010] = two valid bytes in the FIFO.
[011] = three valid bytes in the FIFO.
[100] = four valid bytes in the FIFO.
SPI interrupt status bit.
Set to 1 when an SPI based interrupt occurs.
Cleared after reading SPISTA.
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SPIDIV Register
This 8-bit MMR is the SPI baud rate selection register.
Name:
Address:
Default value:
Access:
SPI Control Register
This 16-bit MMR configures the SPI peripheral in both master
and slave modes.
Name:
Address:
Default value:
Access:
SPIDIV
0xFFFF0A0C
0x00
Read and write
SPICON
0xFFFF0A10
0x0000
Read and write