ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 81

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

Name:
Address:
Default value:
Access:
IRQEN Register
IRQEN provides the value of the current enable mask. When
a bit is set to 1, the corresponding source request is enabled
to create an IRQ exception. When a bit is set to 0, the corre-
sponding source request is disabled or masked, which does not
create an IRQ exception. The IRQEN register cannot be used to
disable an interrupt.
Name:
Address:
Default value:
Access:
IRQCLR Register
IRQCLR is a write-only register that allows the IRQEN register
to clear to mask an interrupt source. Each bit that is set to 1
clears the corresponding bit in the IRQEN register without
affecting the remaining bits. The pair of registers, IRQEN and
IRQCLR, allows independent manipulation of the enable mask
without requiring an atomic read-modify-write.
Use this register to disable an interrupt source only when:
•
•
Do not use the IRQCLR to disable an IRQ source if that IRQ
source has an interrupt pending or could have an interrupt
pending.
Name:
Address:
Default value:
Access:
IRQSTA Register
IRQSTA is a read-only register that provides the current enabled
IRQ source status (effectively a logic AND of the IRQSIG and
IRQEN bits). When set to 1, that source generates an active IRQ
request to the ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
The device is in the interrupt sources interrupt service
routine.
The peripheral is temporarily disabled by its own control
register.
IRQSIG
0x00000000
Read only
IRQCLR
0x00000000
Write only
0xFFFF0004
0xFFFF000C
IRQEN
0xFFFF0008
0x00000000
Read and write
Rev. 0 | Page 81 of 96
Name:
Address:
Default value:
Access:
FAST INTERRUPT REQUEST (FIQ)
The fast interrupt request (FIQ) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface and provides the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.
Bit 31 to Bit 1 of FIQSTA are logically OR’ e d to create the FIQ
signal to the core and to Bit 0 of both the FIQ and IRQ registers
(FIQ source).
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to 1
in FIQEN clears, as a side effect, the same bit in IRQEN. Likewise,
a bit set to 1 in IRQEN clears, as a side effect, the same bit in
FIQEN. An interrupt source can be disabled in both IRQEN
and FIQEN masks.
FIQSIG Register
FIQSIG reflects the status of the different FIQ sources. If a
peripheral generates an FIQ signal the corresponding bit in
the FIQSIG is set, otherwise it is cleared. The FIQSIG bits are
cleared when the interrupt in the particular peripheral is
cleared. All FIQ sources can be masked in the FIQEN MMR.
FIQSIG is read only.
Name:
Address:
Default value:
Access:
FIQEN Register
FIQEN provides the value of the current enable mask. When a
bit is set to 1, the corresponding source request is enabled
to create an FIQ exception. When a bit is set to 0, the corre-
sponding source request is disabled or masked, which does not
create an FIQ exception. The FIQEN register cannot be used to
disable an interrupt.
FIQEN Register
Name:
Address:
Default value:
Access:
FIQSIG
0xFFFF0104
0x00000000
Read only
FIQEN
0xFFFF0108
0x00000000
Read and write
IRQSTA
0xFFFF0000
0x00000000
Read only
ADuC7121