ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 85

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

FIQVEC Register
The FIQ interrupt vector register, FIQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active FIQ. Read this register only when an FIQ
occurs and FIQ interrupt nesting has been enabled by setting
Bit 1 of the IRQCONN register.
Name:
Address:
Default value:
Access:
Table 117. FIQVEC MMR Bit Designations
Bit
31:23
22:7
6:2
1:0
FIQSTAN Register
If IRQCONN.1 is asserted and FIQVEC is read, then one of
these bits assert. The bit that asserts depends on the priority of
the FIQ. If the FIQ is of Priority 0, then Bit 0 asserts; if Priority 1,
then Bit 1 asserts, and so forth.
When a bit is set in this register, all interrupts of that priority
and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit at a time. For
Table 119. IRQCONEMMR Bit Designations
Bit
31:12
11:10
9:8
7:6
Type
Read only
Read and
write
Reserved
Value
11
10
01
00
11
10
01
00
11
10
01
00
Initial
Value
0
0
0
0
FIQVEC
0xFFFF011C
0x00000000
Read only
Description
Always read as 0.
IRQBASE register value.
Highest priority source. This is a
value between 0 and 27
representing the possible
interrupt sources. For example, if
the highest currently active FIQ is
Timer2, then these bits are
[00100].
Reserved bits.
Name
Reserved
IRQ5SRC[1:0]
IRQ4SRC[1:0]
IRQ3SRC[1:0]
Description
These bits are reserved and should not be written to.
External IRQ5 triggers on falling edge.
External IRQ5 triggers on rising edge.
External IRQ5 triggers on low level.
External IRQ5 triggers on high level.
External IRQ4 triggers on falling edge.
External IRQ4 triggers on rising edge.
External IRQ4 triggers on low level.
External IRQ4 triggers on high level.
External IRQ3 triggers on falling edge.
External IRQ3 triggers on rising edge.
External IRQ3 triggers on low level.
External IRQ3 triggers on high level.
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example if this register is set to 0x09 then writing 0xFF changes
the register to 0x08, and writing 0xFF a second time changes
the register to 0x00.
Name:
Address:
Default value:
Access:
Table 118. FIQSTAN MMR Bit Designations
Bit
31:8
7:0
EXTERNAL INTERRUPTS (IRQ0 TO IRQ3)
The ADuC7121 provides up to six external interrupt sources.
These external interrupts can be individually configured as level
or rising/falling edge triggered.
To enable the external interrupt source, first, the appropriate bit
must be set in the FIQEN or IRQEN register. To select the
required edge or level to trigger on, the IRQCONE register
must be appropriately configured.
To properly clear an edge based external IRQ interrupt, set the
appropriate bit in the IRQCLRE register.
IRQCONE Register
Name:
Address:
Default value:
Access:
Name
Reserved
FIQSTAN
0xFFFF013C
0x00000000
Read and write
Description
These bits are reserved and should not be
written to.
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
IRQCONE
0xFFFF0034
0x00000000
Read and write
ADuC7121