ADUC7060 Analog Devices, ADUC7060 Datasheet

Page 1

... Fully specified for −40°C to +125°C operation 32-lead LFCSP (5 mm × 5 mm) 48-lead LFCSP and LQFP Derivatives 32-lead LFCSP (ADuC7061) 48-lead LQFP and 48-lead LFCSP (ADuC7060) APPLICATIONS Industrial automation and process control Intelligent, precision sensing systems loop-based smart sensors ...

Page 2

... ADuC7060/ADuC7061 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 Electrical Specifications............................................................... 5 Timing Specifications ................................................................ 10 Absolute Maximum Ratings.......................................................... 14 ESD Caution................................................................................ 14 Pin Configurations and Function Descriptions ......................... 15 Terminology .................................................................................... 20 Overview of the ARM7TDMI Core............................................. 21 Thumb Mode (T)........................................................................ 21 Multiplier (M) ............................................................................. 21 EmbeddedICE (I) ....................................................................... 21 ARM Registers ............................................................................ 21 Interrupt Latency ...

Page 3

... Table 82, and Figure 26...................................................................73 Changes to Table 84 Column Headings .......................................75 Changes to Table 92 ........................................................................82 Changes to Bit 1, Table 102............................................................90 Changes to Bit 11 Description, Table 105 ....................................95 Changes to SPIMDE Bit Description, Table 106.........................97 Updated Outline Dimensions......................................................103 Changes to Ordering Guide.........................................................104 4/09—Revision 0: Initial Version Rev Page 3 of 108 ADuC7060/ADuC7061     ...

Page 4

... REFERENCE 14-BIT TEMP BUF DAC SENSOR Figure 1. Rev Page 4 of 108 MEMORY POR 32kB FLASH RESET 4kB RAM XTALI ON-CHIP MCU OSC (3%) XTALO PLL 10MHz GPIO PORT WDT UART PORT SPI PORT 2 PWM I C PORT VIC (VECTORED INTERRUPT CONTROLLER) ADuC7060/ ADuC7061 ...

Page 5

... Hz) 24 ADC −27 −2.7 −1 −2 84.7 56 ≤ 1 kHz) 24 ADC ≤ 666 Hz) 24 ADC −120 −1.5 −1 − Rev Page 5 of 108 ADuC7060/ADuC7061 Typ Max Unit 8000 Hz 2600 Hz 650 Hz Bits Bits ±15 ppm of FSR ±8 +27 μV ±0.5 +2.7 μV 650/PGA_GAIN nV/°C 10 nV/° ...

Page 6

... ADuC7060/ADuC7061 Parameter Test Conditions/Comments ADC SPECIFICATIONS: ANALOG Internal V INPUT Main Channel Absolute Input Voltage Range Applies to both VIN+ and VIN− Input Voltage Range Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain = 32 Gain = 64 Gain = 128 Common Mode Voltage gain = 4 to 128 ...

Page 7

... RESET Timeout from POR Maximum supply ramp between 1.8 V and 2.25 V; after POR trip, DVDD must reach 2.25 V within this time limit Min 0.1 = 100 range (reference = 1 range (reference = 1.2 V) Rev Page 7 of 108 ADuC7060/ADuC7061 Typ Max Unit AVDD V 0 REF AVDD − 0.2 V Bits ±2 LSB ± ...

Page 8

... ADuC7060/ADuC7061 Parameter Test Conditions/Comments EXCITATION CURRENT SOURCES Output Current Available from each current source Initial Tolerance at 25°C 1 Drift Initial Current Matching at 25°C Matching between both current sources 1 Drift Matching 1 Line Regulation (AVDD) AVDD = 2.5 V ± 5% Output Compliance 1 WATCHDOG TIMER (WDT) ...

Page 9

... Typical additional supply current consumed during Flash/EE memory program and erase cycles and 5 mA, respectively. Min 2.375 2.375 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature. J Rev Page 9 of 108 ADuC7060/ADuC7061 Typ Max Unit 2.5 2.625 V 2.5 2 ...

Page 10

... ADuC7060/ADuC7061 TIMING SPECIFICATIONS Timing 2 Table 2. I C® Timing in Standard Mode (100 kHz) Parameter Description t SCLOCK low pulse width L t SCLOCK high pulse width H t Start condition hold time SHD t Data setup time DSU t Data hold time DHD t Setup time for repeated start ...

Page 11

... MSB BITS MSB IN BITS DSU t DHD Figure 3. SPI Master Mode Timing (Phase Mode = 1) Min 1 1 × t UCLK 1 2 × t UCLK Rev Page 11 of 108 ADuC7060/ADuC7061 Typ Max (SPIDIV + 1) × t HCLK (SPIDIV + 1) × t HCLK 25 UCLK UCLK ...

Page 12

... ADuC7060/ADuC7061 SCLOCK (POLARITY = 0) SCLOCK (POLARITY = 1) t DOSU MOSI MISO t DSU Table 5. SPI Slave Mode Timing (Phase Mode = 1) Parameter Description SCLOCK edge SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data input setup time before SCLOCK edge ...

Page 13

... DAV MSB BITS MSB IN BITS DHD Figure 6. SPI Slave Mode Timing (Phase Mode = 0) Rev Page 13 of 108 ADuC7060/ADuC7061 Typ Max ) UCLK (SPIDIV + 1) × t HCLK (SPIDIV + 1) × t HCLK SFS ...

Page 14

... ADuC7060/ADuC7061 ABSOLUTE MAXIMUM RATINGS T = −40°C to +125°C, unless otherwise noted. A Table 7. Parameter AGND to DGND to AVDD to DVDD Digital I/O Voltage to DGND VREF± to AGND ADC Inputs to AGND ESD (Human Body Model) Rating All Pins Storage Temperature Junction Temperature Transient Continuous Lead Temperature ...

Page 15

... PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS P1.0/IRQ1/SIN/T0 ADC5/EXT_REF2IN− NOTES 1. THE LFCSP_VQ ONLY HAS AN EXPOSED PADDLE THAT MUST BE LEFT UNCONNECTED. THIS DOES NOT APPLY TO THE LQFP. Table 8. ADuC7060 Pin Function Descriptions Pin No. Mnemonic Type RESET I 2 TMS I 3 P1.0/IRQ1/SIN/T0 I/O 4 P1.1/SOUT I/O 5 P1.2/SYNC ...

Page 16

... ADuC7060/ADuC7061 Pin No. Mnemonic Type 12 ADC5/EXT_REF2IN− ADC4/EXT_REF2IN ADC3 I 15 ADC2 I 16 IEXC1 O 17 IEXC0 O 18 GND_SW I 19 ADC1 I 20 ADC0 I 21 VREF VREF− AGND S 24 AVDD S 25 ADC6 I 26 ADC7 I 27 ADC8 I 28 ADC9 I 29 DGND ...

Page 17

... Digital Supply Pin. JTAG Reset/Boot Mode. Input pin used for debug and download only and boot mode (BM). The ADuC7060 enters serial download mode low at reset and executes code pulled high at reset through a 13 kΩ resistor. JTAG Data Out. Output pin used for debug and download only. ...

Page 18

... ADuC7060/ADuC7061 ADC5/EXT_REF2IN− ADC4/EXT_REF2IN+ NOTES 1. THE 32-LEAD LFCSP_VQ HAS AN EXPOSED PADDLE. THIS EXPOSED Table 9. ADuC7061 Pin Function Descriptions Pin No. Mnemonic Type RESET I 2 TMS I 3 P1.0/IRQ1/SIN/T0 I/O 4 P1.1/SOUT I/O 5 DAC0 O 6 ADC5/EXT_REF2IN− ADC4/EXT_REF2IN ADC3 I 9 ADC2 I 10 IEXC1 O 11 ...

Page 19

... JTAG Data In. Input pin used for debug and download only. Add an external pull-up resistor (~100 kΩ) to this pin. JTAG Clock. Input pin used for debug and download only. Add an external pull-up resistor (~100 kΩ) to this pin. Rev Page 19 of 108 ADuC7060/ADuC7061 2 C ...

Page 20

... ADuC7060/ADuC7061 TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC, when the ADC has settled. The sigma-delta (Σ-Δ) conversion techniques used on this part mean that whereas the ADC front-end signal is oversampled at a relatively high sample rate, a subsequent digital filter is used to decimate the output, giving a valid 24-bit data conversion result at output rates from kHz ...

Page 21

... RAM area and descends using the area as required. A separate stack is defined for each of the exceptions. The size of each stack is user configurable and is dependent on the target application. When programming using high level languages, Rev Page 21 of 108 ADuC7060/ADuC7061 Address 0x00 0x10 0x1C ...

Page 22

... ADuC7060/ADuC7061 such necessary to ensure that the stack does not overflow. This is dependent on the performance of the compiler that is used. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14) as represented in Figure 9 ...

Page 23

... Cleared by user to disable the Flash/EE interrupt. 3 Erase/write command protection. Set by user to enable the erase and write commands. Cleared to protect the Flash/EE against the erase/write command. 2:0 Reserved. Always set these bits to 0. Rev Page 23 of 108 ADuC7060/ADuC7061 ...

Page 24

... ADuC7060/ADuC7061 FEECON Register FEECON is an 8-bit command register. The commands are described in Table 15. Table 15. Command Codes in FEECON Code Command Description 1 0x00 Null Idle state. 1 0x01 Single read Load FEEDAT with the 16-bit data. Indexed by FEEADR. 1 0x02 Single write Write FEEDAT at the address pointed to by FEEADR. This operation takes 50 μs. ...

Page 25

... FEEPRO write sequence is saved one time only and must be used for any subsequent access of the FEEHID or FEEPRO MMRs. A mass erase sets the software protection key back to 0xFFFF but also erases the entire user code space. Rev Page 25 of 108 ADuC7060/ADuC7061 FEEHIDE 0xFFFF0E20 0xFFFFFFFF Read and write ...

Page 26

... ADuC7060/ADuC7061 Permanent Protection Permanent protection can be set via FEEPRO, similar to how keyed permanent protection is set, with the only difference being that the software key used is 0xDEADDEAD. When the FEEPRO write sequence is saved, only a mass erase sets the software protection key back to 0xFFFFFFFF. This also erases the entire user code space ...

Page 27

... Figure 12. Memory Mapped Registers Rev Page 27 of 108 ADuC7060/ADuC7061 PWM FLASH CONTROL INTERFACE GPIO SPI UART DAC ADC BAND GAP REFERENCE 2 SPI/I C SELECTION PLL AND OSCILLATOR ...

Page 28

... ADuC7060/ADuC7061 COMPLETE MMR LISTING In the following MMR tables, addresses are listed in hexadecimal code. Access types include R for read, W for write, and R/W for read and write. Table 17. IRQ Address Base = 0xFFFF0000 Address Name Bytes 0x0000 IRQSTA 4 0x0004 IRQSIG 4 0x0008 IRQEN 4 0x000C IRQCLR ...

Page 29

... PLL clock source selection MMR. 0xXXXX PLLCON postwrite key. 0xXXXX POWCON1 prewrite key. 0x124 Power control register. 0xXXXX POWCON1 postwrite key. 0xXXXX GP0CON1 prewrite key. 0x00 Configures P0.0, P0.1, P0.2, and P0.3 as analog inputs or digital I/Os. Also 2 enables SPI mode. 0xXXXX GP0CON1 postwrite key. Rev Page 29 of 108 ADuC7060/ADuC7061 ...

Page 30

... ADuC7060/ADuC7061 Table 21. ADC Address Base = 0xFFFF0500 Access Address Name Bytes Type 0x0500 ADCSTA 2 R 0x0504 ADCMSKI 2 R/W 0x0508 ADCMDE 1 R/W 0x050C ADC0CON 2 R/W 0x0510 ADC1CON 2 R/W 0x0514 ADCFLT 2 R/W 0x0518 ADCCFG 1 R/W 0x051C ADC0DAT 4 R 0x0520 ADC1DAT 0x0524 ADC0OF 2 R/W 1 0x0528 ADC1OF 2 R/W 0x052C ADC0GN 1 2 R/W 1 0x0530 ...

Page 31

... GPIO Port 1 data clear MMR. 0x00000000 GPIO Port 1 pull-up disable MMR. 0x000000XX GPIO Port 2 data control MMR. 0x000000XX GPIO Port 2 data set MMR. 0x000000XX GPIO Port 2 data clear MMR. 0x00000000 GPIO Port 2 pull-up disable MMR. Rev Page 31 of 108 ADuC7060/ADuC7061 ...

Page 32

... ADuC7060/ADuC7061 Table 27. Flash/EE Base Address = 0xFFFF0E00 Access Address Name Bytes Type 0x0E00 FEESTA 2 R 0x0E04 FEEMOD 2 R/W 0x0E08 FEECON 1 R/W 0x0E0C FEEDAT 2 R/W 0x0E10 FEEADR 2 R/W 0x0E18 FEESIGN 3 R 0x0E1C FEEPRO 4 R/W 0x0E20 FEEHIDE 4 R/W Table 28. PWM Base Address = 0xFFFF0F80 Access Address Name Bytes Type 0x0F80 PWMCON ...

Page 33

... Reset All External MMRs Peripherals (Excluding RSTSTA) Reset Yes Yes Yes Yes Yes Yes Yes Yes Rev Page 33 of 108 ADuC7060/ADuC7061 1 RSTSTA Watchdog RAM (Status After Timer Reset Valid Reset Event) Yes Yes/No RSTSTA[ Yes RSTSTA[ ...

Page 34

... ADuC7060/ADuC7061 OSCILLATOR, PLL, AND POWER CONTROL CLOCKING SYSTEM The ADuC706x integrates a 32.768 kHz ±3% oscillator, a clock divider, and a PLL. The PLL locks onto a multiple of the inter- nal oscillator or an external 32.768 kHz crystal to provide a stable 10.24 MHz clock (UCLK) for the system. To allow power saving, the core can operate at this frequency or at binary submultiples of it ...

Page 35

... POWCON0. Name: Address: Default value: Access: Function and UART serial ports. Rev Page 35 of 108 ADuC7060/ADuC7061 POWCON0 0xFFFF0408 0x7B Read and write This register controls the clock divide bits controlling the CPU clock (HCLK). ...

Page 36

... ADuC7060/ADuC7061 Name: POWKEY1 Address: 0xFFFF0404 Default value: 0xXXXX Access: Write Function: When writing to POWCON0, the value of 0x01 must be written to this register in the instruction immediately before writing to POWCON0. Name: POWKEY2 Address: 0xFFFF040C Default value: 0xXXXX Access: Write Function: When writing to POWCON0, the value of ...

Page 37

... Table 35. PLLCON MMR Bit Designations Bit 7:3 2 1:0 Name: Address: Default value: Access: Function: Rev Page 37 of 108 ADuC7060/ADuC7061 IRQ0 to IRQ3 Start-Up/Power-On Time Yes 130 Yes 4.8 μ 660 μ Yes 4.8 μ 660 μ Yes 66 μ 900 μ Yes 66 μ ...

Page 38

... ADuC7060/ADuC7061 ADC CIRCUIT INFORMATION INTERNAL REFERENCE IEXC0 IEXC1 ADC0 ADC1 CHOP MUX ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GND_SW 50Ω AGND TEMPERATURE The ADuC706x incorporates two independent multichannel Σ-Δ ADCs. The primary ADC is a 24-bit, 4-channel ADC. The auxiliary ADC is a 24-bit Σ ...

Page 39

... ADC0DIAG[1:0] bits in the ADC0CON register. Similarly, the diagnostic current sources for the auxiliary ADC analog inputs are controlled by the ADC1DIAG[1:0] bits in the ADC1CON register. Rev Page 39 of 108 ADuC7060/ADuC7061 ±37.5 mV ±18.75 mV ±9.375 mV ±4.68 mV (PGA = 32) (PGA = 64) ...

Page 40

... ADuC7060/ADuC7061 Table 39. Example Scenarios for Using Diagnostic Current Sources Diagnostic Test Register Setting Description ADC0DIAG[1: Convert ADC0/ADC1 as normal with diagnostic currents disabled. ADC0DIAG[1: Enable a 50 μA diagnostic current source on ADC0 by setting ADC0DIAG[1: Convert ADC0 and ADC1. Convert ADC0 in single-ended mode with diagnostic currents disabled. ...

Page 41

... ADC conversion result even though the ready bits are not cleared. ADC Status Register Name: Address: Default value: Access: Function: 80 100 120 140 Rev Page 41 of 108 ADuC7060/ADuC7061 ADCSTA 0xFFFF0500 0x0000 Read only This read-only register holds general status information related to the mode of operation or current status of the ADuC706x ADCs. ...

Page 42

... ADuC7060/ADuC7061 Table 40. ADCSTA MMR Bit Designations Bit Name Description 15 ADCCALSTA ADC calibration status. This bit is set automatically in hardware to indicate that an ADC calibration cycle has been completed. This bit is cleared after ADCMDE is written to. 14 Not used. This bit is reserved for future functionality. ...

Page 43

... Not used. This bit is reserved for future functionality and should not be monitored by user code. 5 ADCLPMEN Enable low power mode. This bit has no effect if ADCMDE[4: (ADC is in normal mode). This bit must be set low power mode. Clearing this bit in low power mode results in erratic ADC results. Rev Page 43 of 108 ADuC7060/ADuC7061 ...

Page 44

... ADuC7060/ADuC7061 Bit Name Description 4:3 ADCLPMCFG[1:0] ADC power mode configuration. [00] = ADC normal mode. If enabled, the ADC operates with normal current consumption yielding optimum electrical performance. [01] = ADC low power mode. [10] = ADC normal mode, same as [00]. [11] = ADC low power plus mode (low power mode and PGA off ). ...

Page 45

... ADC0 gain of 16. [0101] = ADC0 gain of 32. [0110] = ADC0 gain of 64 (maximum PGA gain setting). [0111] = ADC0 gain of 128 (extra gain implemented digitally). [1000] = ADC0 gain of 256. [1001] = ADC0 gain of 512. [1XXX] = ADC0 gain is undefined. Rev Page 45 of 108 ADuC7060/ADuC7061 ...

Page 46

... ADuC7060/ADuC7061 Auxiliary ADC Control Register Name: ADC1CON Address: 0xFFFF0510 Default value: 0x0000 Access: Read and write Function: The auxiliary ADC control MMR is a 16-bit register. Table 44. ADC1CON MMR Bit Designations Bit Name Description 15 ADC1EN Auxiliary channel ADC enable. This bit is set user code to enable the auxiliary ADC. ...

Page 47

... Cleared by user to disable the running average function. 13:8 AF[5:0] Averaging factor (AF). The values written to these bits are used to implement a programmable first-order sinc3 post filter. The averaging factor can further reduce ADC noise at the expense of output rate as described in Bits[6:0] (sinc3 decimation factor) in this table. Rev Page 47 of 108 ADuC7060/ADuC7061 ...

Page 48

... ADuC7060/ADuC7061 Bit Name Description 7 NOTCH2 Sinc3 modify. Set by user to modify the standard sinc3 frequency response to increase the filter stop-band rejection by approximately 5 dB. This is achieved by inserting a second notch (NOTCH2 1.333 × f NOTCH2 where f is the location of the first notch in the response. ...

Page 49

... Set enable a 20 kΩ resistor in series with the ground switch. Clear this bit to disable this resistor. 0 ADCRCEN ADC result counter enable. Set by user to enable the result count mode. ADC interrupts occur if ADC0RCR = ADC0RCV. Cleared to disable the result counter. ADC interrupts occur after every conversion. Rev Page 49 of 108 ADuC7060/ADuC7061 ...

Page 50

... ADuC7060/ADuC7061 Primary Channel ADC Data Register Name: ADC0DAT Address: 0xFFFF051C Default value: 0x00000000 Access: Read only Function: This ADC data MMR holds the 24-bit conversion result from the primary ADC. The ADC does not update this MMR if the ADC0 conversion result ready bit (ADCSTA[0]) is set ...

Page 51

... The result counter is enabled via ADCCFG[0]. This MMR is also reset to 0 when the primary ADC is reconfigured, that is, when the ADC0CON or ADCMDE is written. Table 56. ADC0RCV MMR Bit Designations Bits Description 15:0 ADC0 result counter register. Rev Page 51 of 108 ADuC7060/ADuC7061 ...

Page 52

... ADuC7060/ADuC7061 Primary Channel ADC Threshold Register Name: ADC0TH Address: 0xFFFF053C Default value: 0x0000 Access: Read and write Function: This 16-bit MMR sets the threshold against which the absolute value of the primary ADC conversion result is compared. In unipolar mode, ADC0TH[15:0] are compared, and in twos complement mode, ADC0TH[14:0] are compared ...

Page 53

... FAST OVERRANGE 16 ADC0ACC ACCUMULATOR f ADC ADC (READABLE) ADC0ATH |ABSVAL| INTERRUPT ≥ ≥ (ADC0RDY) f ADC ADC0TH Rev Page 53 of 108 ADuC7060/ADuC7061 Description ADC0 32-bit comparator threshold register of the accumulator. (READABLE) 32 INTERRUPT ≥ (ADC0ATHEX) ADC0THV UP/DOWN OPTION: UP/RESET INTERRUPT ≥ (ADC0THEX) ADC0THC ...

Page 54

... ADuC7060/ADuC7061 Excitation Current Sources Control Register Name: IEXCON Address: 0xFFFF0570 Default value: 0x00 Access: Read and write Function: This 8-bit MMR controls the two excitation current sources, IEXC0 and IEXC1. Table 62. IEXCON MMR Bit Designations Bit Name Description 7 IEXC1_EN Enable bit for IEXC1 current source. ...

Page 55

... C UART AD592 ADC4 GPIO ADR280 VREF+ VREF– AGND/DGND Figure 19. Example of a Thermocouple Interface Circuit RTD Figure 20. Example of an RTD Interface Circuit +2.5V Rev Page 55 of 108 ADuC7060/ADuC7061 ADuC7060/ ADuC7061 +2.5V IEXC1 AVDD/DVDD ADC0 SPI UART ADC1 GPIO VREF+ VREF– AGND/DGND ...

Page 56

... ADuC7060/ADuC7061 DAC PERIPHERALS DAC The ADuC706x incorporates a voltage output DAC on chip. In normal mode, the DAC resolution is 12-bits. In interpolation, the DAC resolution is 16 bits with 14 effective bits. The DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. The DAC has four selectable ranges. ...

Page 57

... DAC itself disabled. ADC6 is the positive input to the op amp, ADC7 is the negative input, and ADC8 is the output. In this mode, the DAC should be powered down by setting Bit 9 of DAC0CON. Rev Page 57 of 108 ADuC7060/ADuC7061 in this case, not REF AVDD 100mV ...

Page 58

... ADuC7060/ADuC7061 NONVOLATILE FLASH/EE MEMORY The ADuC706x incorporates Flash/EE memory technology on chip to provide the user with nonvolatile, in-circuit reprogram- mable memory space. Like EEPROM, flash memory can be programmed in-system at a byte level, although it must first be erased. The erase is performed in page blocks result, flash memory is often and, more correctly, referred to as Flash/EE memory ...

Page 59

... Each bit that is set to 1 clears the corresponding bit in the IRQEN register without affecting the remaining bits. The pair of registers, IRQEN and IRQCLR, allows independent manipulation of the enable mask without requiring an atomic read-modify-write. Clear to 0 has no effect. Rev Page 59 of 108 ADuC7060/ADuC7061 ...

Page 60

... ADuC7060/ADuC7061 IRQCLR Register Name: IRQCLR Address: 0xFFFF000C Default value: 0x00000000 Access: Write only IRQSTA IRQSTA is a read-only register that provides the current enabled IRQ source status (effectively a logic AND of the IRQSIG and IRQEN bits). When set to 1, that source generates an active IRQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation ...

Page 61

... IRQ. This register should be read only when an IRQ occurs and IRQ interrupt nesting has been enabled by setting Bit 0 of the IRQCONN register. IRQVEC Register Name: IRQVEC Address: 0xFFFF001C Default value: 0x00000000 Access: Read only Rev Page 61 of 108 ADuC7060/ADuC7061 Description Always read as 0. Vector base address. ...

Page 62

... ADuC7060/ADuC7061 Table 68. IRQVEC MMR Bit Designations Initial Bit Access Value Description 31:23 Read 0 Always read as 0. only 22:7 Read 0 IRQBASE register value. only 6:2 Read 0 Highest priority IRQ source. This only is a value between repre- senting the possible interrupt sources. For example, if the highest currently active IRQ is Timer1, then these bits are [01000] ...

Page 63

... Read only 0 6:2 0 1:0 Reserved 0 Rev Page 63 of 108 ADuC7060/ADuC7061 Description Always read as 0. IRQBASE register value. Highest priority FIQ source. This is a value between that represents the possible interrupt sources. For example, if the highest currently active FIQ is Timer1, then these bits are [01000] ...

Page 64

... ADuC7060/ADuC7061 FIQSTAN If IRQCONN[1] is asserted and FIQVEC is read, then one of these bits asserts. The bit that asserts depends on the priority of the FIQ. If the FIQ is of Priority 0, Bit 0 asserts; Priority 1, Bit 1 asserts; and so forth. When a bit is set in this register, all interrupts of that priority and lower are blocked ...

Page 65

... A 1 must be written to this bit in the IRQ1 interrupt service routine to clear an edge triggered IRQ1 interrupt. 13 IRQ0CLRI A 1 must be written to this bit in the IRQ0 interrupt service routine to clear an edge triggered IRQ0 interrupt. 12:0 Reserved These bits are reserved and should not be written to. Rev Page 65 of 108 ADuC7060/ADuC7061 ...

Page 66

... ADuC7060/ADuC7061 TIMERS The ADuC706x features four general-purpose timer/counters. • Timer0 • Timer1 or wake-up timer • Timer2 or watchdog timer • Timer3 The four timers in their normal mode of operation can be either free running or periodic. In free running mode, the counter decrements/increments from the maximum or minimum value until zero/full scale and starts again at the maximum or minimum value ...

Page 67

... OR 32,768 UP/DOWN COUNTER TIMER0 VALUE CAPTURE IRQ[31:0] Figure 23. Timer0 Block Diagram Rev Page 67 of 108 ADuC7060/ADuC7061 T0LD 0xFFFF0320 0x00000000 Read and write T0LD is a 32-bit register that holds the 32-bit value that is loaded into the counter. T0CLRI 0xFFFF032C ...

Page 68

... ADuC7060/ADuC7061 Timer0 Capture Register Name: T0CAP Address: 0xFFFF0330 Default value: 0x00000000 Access: Read only Function: This 32-bit register holds the 32-bit value captured by an enabled IRQ event. Timer0 Control Register Name: T0CON Address: 0xFFFF0328 Default value: 0x01000000 Access: Read and write Function: This 32-bit MMR configures the mode of operation of Timer0 ...

Page 69

... This 8-bit, write-only MMR is written (with any value) by user code to clear the interrupt. Timer1 Value Register Name: T1VAL Address: 0xFFFF0344 Default value: 0xFFFFFFFF Access: Read only Function: T1VAL is a 32-bit register that holds the current value of Timer1. Rev Page 69 of 108 ADuC7060/ADuC7061 ...

Page 70

... ADuC7060/ADuC7061 32.768kHz OSCILLATOR CORE CLOCK FREQUENCY/CD EXTERNAL 32.768kHz WATCH CRYSTAL Timer1 Control Register Name: T1CON Address: 0xFFFF0348 Default value: 0x0000 Access: Read and write Function: This 16-bit MMR configures the mode of operation of Timer1. Table 80. T1CON MMR Bit Designations Bit Name Description 15:11 Reserved ...

Page 71

... WATCHDOG RESET PRESCALER 16-BIT 1, 16, 256 UP/DOWN COUNTER TIMER2 IRQ TIMER2 VALUE Figure 25. Timer2 Block Diagram Rev Page 71 of 108 ADuC7060/ADuC7061 T2LD 0xFFFF0360 0x0040 Read and write This 16-bit MMR holds the Timer2 reload value. T2CLRI 0xFFFF036C Write only This 8-bit, write-only MMR is written (with ...

Page 72

... ADuC7060/ADuC7061 Timer2 Control Register Name: T2CON Address: 0xFFFF0368 Default value: 0x0000 Access: Read and write Function: This 16-bit MMR configures the mode of operation of Timer2, as described in detail in Table 81. Table 81. T2CON MMR Bit Designations Bit Name Description 15:9 Reserved. These bits are reserved and should be written user code. ...

Page 73

... This is a 16-bit register that holds the 16-bit value captured by an enabled IRQ event. Timer3 Control Register Name: T3CON Address: 0xFFFF0388 Default value: 0x00000000 Access: Read and write Function: This 32-bit MMR configures the mode of operation of Timer3. Rev Page 73 of 108 ADuC7060/ADuC7061 ...

Page 74

... ADuC7060/ADuC7061 Table 82. T3CON MMR Bit Designations Bit Name Description 31:18 Reserved. 17 T3CAPEN Event enable bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16:12 T3CAPSEL Event select range 17. The events are described in Table 78. 11 Reserved. 10:9 T3CLKSEL Clock select ...

Page 75

... PWM0COM1. PWMCON Control Register Name: PWMCON Address: 0xFFFF0F80 Default value: 0x0012 Access: Read and write Function: This is a 16-bit MMR that configures the PWM outputs. Rev Page 75 of 108 ADuC7060/ADuC7061 Figure 26. Figure 26. ...

Page 76

... ADuC7060/ADuC7061 Table 84. PWMCON MMR Bit Designations Bit Name Description 15 Reserved This bit is reserved. Do not write to this bit. 14 Sync Enables PWM synchronization. Set user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on the P1.2/SYNC pin. ...

Page 77

... PWM interrupt before exiting the ISR. This prevents generation of multiple interrupts. 1 DIR PWM0 HS1 0 HS1 1 1 Default Value 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Rev Page 77 of 108 ADuC7060/ADuC7061 2 PWM Outputs PWM1 PWM2 HS1 LS1 0 LS1 1 1 HS1 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W PWM3 ...

Page 78

... ADuC7060/ADuC7061 PWM0COM0 Compare Register Name: PWM0COM0 Address: 0xFFFF0F84 Default value: 0x0000 Access: Read and write Function: PWM0 output pin goes high when the PWM timer reaches the count value stored in this register. PWM0COM1 Compare Register Name: PWM0COM1 Address: 0xFFFF0F88 Default value: ...

Page 79

... PWMCLRI Register Name: PWMCLRI Address: 0xFFFF0FB8 Default value: 0x0000 Access: Write only Function: Write any value to this register to clear a PWM interrupt source. This register must be written to before exiting a PWM interrupt service routine; otherwise, multiple interrupts occur. Rev Page 79 of 108 ADuC7060/ADuC7061 ...

Page 80

... ADuC7060/ADuC7061 UART SERIAL INTERFACE Each ADuC706x features a 16450-compatible UART. The UART is a full-duplex, universal, asynchronous receiver/transmitter. A UART performs serial-to-parallel conversion on data characters received from a peripheral device and parallel-to-serial conversion on data characters received from the ARM7TDMI. The UART features a fractional divider that facilitates high accuracy baud rate generation and a network addressable mode ...

Page 81

... Default value: 0x00 Access: Read and write UART Control Register 0 This 8-bit register (COMCON0) controls the operation of the UART in conjunction with COMCON1. COMCON0 Register Name: COMCON0 Address: 0xFFFF070C Default value: 0x00 Access: Read and write Rev Page 81 of 108 ADuC7060/ADuC7061 ...

Page 82

... ADuC7060/ADuC7061 Table 89. COMCON0 MMR Bit Designations Bit Name 7 DLAB 6 BRK EPS 3 PEN 2 Stop 1:0 WLS Description Divisor latch access. Set by user to enable access to the COMDIV0 and COMDIV1 registers. Cleared by user to disable access to COMDIV0 and COMDIV1 and enable access to COMRX, COMTX, and COMIEN0. ...

Page 83

... Set when the stop bit is invalid. Cleared automatically Parity error. Set when a parity error occurs. Cleared automatically Overrun error. Set automatically if data is overwritten before being read. Cleared automatically Data ready. Set automatically when COMRX is full. Cleared by reading COMRX. Rev Page 83 of 108 ADuC7060/ADuC7061 ...

Page 84

... ADuC7060/ADuC7061 UART Status Register 1 COMSTA1 Register Name: COMSTA1 Address: 0xFFFF0718 Default value: 0x00 Access: Read only Function: COMSTA1 is a modem status register. Table 92. COMSTA1 MMR Bit Designations Bit Name Description 7:5 Reserved. Not used. 4 CTS Clear to send. 3:1 Reserved. Not used. 0 DCTS Delta CTS. ...

Page 85

... COMTX or read COMIID0 Read 10:0 FBN[10:0] COMSTA1 register Rev Page 85 of 108 ADuC7060/ADuC7061 Description Fractional baud rate generator enable bit. Set by user to enable the fractional baud rate generator. Cleared by user to generate the baud rate using the standard 450 UART baud rate generator. ...

Page 86

... ADuC7060/ADuC7061 Each ADuC706x incorporates peripheral that can configured as a fully I C-compatible I C bus master device fully I C bus-compatible slave device. The two pins used for data transfer, SDA and SCL, are configured in a wire-AND’ format that allows arbitration in a multimaster system ...

Page 87

... MMR is common to both master and slave modes Master Registers Master Control, I2CMCON Register Name: Address: Default value: Access: Function Rev Page 87 of 108 ADuC7060/ADuC7061 I2CMCON 0xFFFF0900 0x0000 Read and write 2 This 16-bit MMR configures the I C peripheral in master mode. ...

Page 88

... ADuC7060/ADuC7061 Table 96. I2CMCON MMR Bit Designations Bit Name Description 15:9 Reserved. These bits are reserved and should not be written to I2CMCENI I C transmission complete interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I Clear this interrupt source I2CNACKENI acknowledge (NACK) received interrupt enable bit ...

Page 89

... FIFO. [10 byte in master transmit FIFO. 2 [11 master transmit FIFO full status register in master mode bus master does not gain control of the I Rev Page 89 of 108 ADuC7060/ADuC7061 2 C bus. If the I2CALENI bit in I2CMCON is set, an ...

Page 90

... ADuC7060/ADuC7061 Master Receive, I2CMRX, Register Name: I2CMRX Address: 0xFFFF0908 Default value: 0x00 Access: Read only Function: This 8-bit MMR is the I register Master Transmit, I2CMTX, Register Name: I2CMTX Address: 0xFFFF090C Default value: 0x00 Access: Write only Function: This 8-bit MMR is the I register ...

Page 91

... These bits control the duration of the low period of SCL Slave Registers Slave Control, I2CSCON, Register Name: I2CSCON Address: 0xFFFF0928 Default value: 0x0000 Access: Read and write Function: This 16-bit MMR configures the I in slave mode. Rev Page 91 of 108 ADuC7060/ADuC7061 peripheral ...

Page 92

... ADuC7060/ADuC7061 Table 103. I2CSCON MMR Bit Designations Bit Name Description 15:11 Reserved bits. 10 I2CSTXENI Slave transmit interrupt enable bit. Set this bit to enable an interrupt after a slave transmits a byte. Clear this interrupt source. 9 I2CSRXENI Slave receive interrupt enable bit. Set this bit to enable an interrupt after the slave receives data. ...

Page 93

... This bit is set to 1 when the receive FIFO of the slave is not empty. This bit causes an interrupt to occur if the I2CSRXENI bit in I2CSCON is set. The receive FIFO must be read or flushed to clear this bit status register in slave mode. Rev Page 93 of 108 ADuC7060/ADuC7061 ...

Page 94

... ADuC7060/ADuC7061 Bit Name Description 2 2 I2CSTXQ I C slave transmit request bit. This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in I2CSCON is =0, this bit goes high just after the negative edge of SCL during the read bit transmission. If the I2CSETEN bit in I2CSCON is =1, this bit goes high just after the positive edge of SCL during the read bit transmission ...

Page 95

... FIFO full. 2 3:2 I2CSRXSTA I C slave receive FIFO status bits. [00] = FIFO empty [01] = byte written to FIFO [10] = one byte in FIFO [11] = FIFO full 1:0 I2CSTXSTA slave transmit FIFO status bits. [00] = FIFO empty. [01] = byte written to FIFO. [10] = one byte in FIFO. [11] = FIFO full. Rev Page 95 of 108 ADuC7060/ADuC7061 ...

Page 96

... ADuC7060/ADuC7061 SERIAL PERIPHERAL INTERFACE The ADuC706x integrates a complete hardware serial peripheral interface (SPI) on chip. SPI is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex maximum bit rate of 5.12 Mbps. The SPI port can be configured for master or slave operation and typically consists of four pins: MISO, MOSI, SCLK, and SS ...

Page 97

... FIFO. [010 valid bytes in the FIFO. [011 valid bytes in the FIFO. [100 valid bytes in the FIFO. 0 SPIISTA SPI interrupt status bit. Set to 1 when an SPI based interrupt occurs. Cleared after reading SPISTA. Rev Page 97 of 108 ADuC7060/ADuC7061 ...

Page 98

... ADuC7060/ADuC7061 SPI Receive Register SPIRX Register Name: SPIRX Address: 0xFFFF0A04 Default value: 0x00 Access: Read only Function: This 8-bit MMR is the SPI receive register. SPI Transmit Register SPITX Register Name: SPITX Address: 0xFFFF0A08 Default value: 0x00 Access: Write only Function: This 8-bit MMR is the SPI transmit register. ...

Page 99

... Cleared by user, the serial clock idles low. 2 SPICPH Serial clock phase mode bit. Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the serial clock pulses at the end of each serial bit transfer. Rev Page 99 of 108 ADuC7060/ADuC7061 ...

Page 100

... ADuC7060/ADuC7061 Bit Name Description 1 SPIMEN Master mode enable bit. Set by user to enable master mode. Cleared by user to enable slave mode. 0 SPIEN SPI enable bit. Set by user to enable the SPI. Cleared by user to disable the SPI. Rev Page 100 of 108 ...

Page 101

... PWM sync (PWM sync input pin). GPIO PWM trip (PWM trip input pin). GPIO PWM2 (PWM Output 2). GPIO PWM3 (PWM Output 3). GPIO PWM4 (PWM Output 4). GPIO/IRQ2/EXTCLK PWM0 (PWM Output 0). GPIO/IRQ3 PWM5 (PWM Output 5). Default Value 0x00000000 0x00000000 0x00000000 Rev Page 101 of 108 ADuC7060/ADuC7061 Access R/W R/W R/W ...

Page 102

... ADuC7060/ADuC7061 Table 110. GPxCON MMR Bit Designations Bit Description 31:30 Reserved. 29:28 Reserved. 27:26 Reserved. 25:24 Selects the function of the P0.6/RTS and P1.6/PWM pins. 23:22 Reserved. 21:20 Selects the function of the P0.5/CTS and P1.5/PWM3 pins. 19:18 Reserved. 17:16 Selects the function of the P0.4/IRQ0/PWM1 and P1.4/PWM2 pins. 15:14 Reserved. 13:12 Selects the function of the P0.3/MOSI/SDA and P1.3/TRIP pins ...

Page 103

... GP0CON1. Name: GP0KEY2 Address: 0xFFFF046C Default value: 0xXXXX Access: Write only Function: When writing to GP0CON1, the value of 0x13 must be written to this register in the instruction immediately after writing to GP0CON1. Rev Page 103 of 108 ADuC7060/ADuC7061 2 C mode, set this bit to 1. ...

Page 104

... Finally, note that, when the DVDD supply reaches 1 must ramp to 2. less than 128 ms. This is a requirement of the internal power-on reset circuitry. Rev Page 104 of 108 DIGITAL ANALOG BEAD SUPPLY SUPPLY + – 10µF 10µF ADuC7060/ ADuC7061 AVDD DVDD 0.1µF AGND DGND Figure 29. External Single Supply Connections 0.1µF ...

Page 105

... TYP 0.05 MAX 0.02 NOM COPLANARITY 0.50 BSC 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 31. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ × Body, Very Thin Quad (CP-48-3) Dimensions shown in millimeters Rev Page 105 of 108 ADuC7060/ADuC7061 0.60 MAX PIN 1 INDICATOR EXPOSED 3.65 PAD 3.50 SQ (BOTTOM VIEW) 3.35 ...

Page 106

... Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] ADuC7060 Quick Start Plus Development System ADuC7061 Quick Start Evaluation System Rev Page 106 of 108 ...

Page 107

... NOTES Rev Page 107 of 108 ADuC7060/ADuC7061 ...

Page 108

... ADuC7060/ADuC7061 NOTES ©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07079-0-5/11(C) Rev Page 108 of 108 ...