ADUC7028 Analog Devices, ADUC7028 Datasheet - Page 47

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ADUC7028

Manufacturer Part Number
ADUC7028
Description
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7028

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Flash (kbytes)
62Bytes
Sram (bytes)
8192Bytes
Gpio Pins
40
Adc # Channels
8

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NONVOLATILE FLASH/EE MEMORY
The ADuC7019/20/21/22/24/25/26/27/28/29 incorporate
Flash/EE memory technology on-chip to provide the user with
nonvolatile, in-circuit reprogrammable memory space.
Like EEPROM, flash memory can be programmed in-system
at a byte level, although it must first be erased. The erase is
performed in page blocks. As a result, flash memory is often
and more correctly referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the
ideal memory device that includes nonvolatility, in-circuit
programmability, high density, and low cost. Incorporated in
the ADuC7019/20/21/22/24/25/26/27/28/29, Flash/EE memory
technology allows the user to update program code space in-
circuit, without the need to replace one-time programmable
(OTP) devices at remote operating nodes.
Each part contains a 64 kB array of Flash/EE memory. The
lower 62 kB is available to the user and the upper 2 kB contain
permanently embedded firmware, allowing in-circuit serial
download. These 2 kB of embedded firmware also contain a
power-on configuration routine that downloads factory-
calibrated coefficients to the various calibrated peripherals
(such as ADC, temperature sensor, and band gap references).
This 2 kB embedded firmware is hidden from user code.
Flash/EE Memory Reliability
The Flash/EE memory arrays on the parts are fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as
1.
2.
3.
4.
In reliability qualification, every half word (16-bit wide)
location of the three pages (top, middle, and bottom) in the
Flash/EE memory is cycled 10,000 times from 0x0000 to
0xFFFF. As indicated in Table 1, the Flash/EE memory
endurance qualification is carried out in accordance with
JEDEC Retention Lifetime Specification A117 over the
industrial temperature range of −40° to +125°C. The results
allow the specification of a minimum endurance figure over a
supply temperature of 10,000 cycles.
Initial page erase sequence
Read/verify sequence (single Flash/EE)
Byte program sequence memory
Second read/verify sequence (endurance cycle)
Rev. D | Page 47 of 96
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the parts are
qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature
(T
Flash/EE memory is cycled to its specified endurance limit,
described in Table 1, before data retention is characterized. This
means that the Flash/EE memory is guaranteed to retain its data
for its fully specified retention lifetime every time the Flash/EE
memory is reprogrammed. In addition, note that retention
lifetime, based on an activation energy of 0.6 eV, derates with T
as shown in Figure 51.
PROGRAMMING
The 62 kB of Flash/EE memory can be programmed in-circuit,
using the serial download mode or the provided JTAG mode.
Serial Downloading (In-Circuit Programming)
The ADuC7019/20/21/22/24/25/26/27/28/29 facilitate code
download via the standard UART serial port or via the I
The parts enter serial download mode after a reset or power
cycle if the BM pin is pulled low through an external 1 kΩ
resistor. After a part is in serial download mode, the user can
download code to the full 62 kB of Flash/EE memory while the
device is in-circuit in its target application hardware. An
executable PC serial download is provided as part of the
development system for serial downloading via the UART. The
AN-806 Application Note describes the protocol for serial
downloading via the UART and I
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate
code download and debug.
ADuC7019/20/21/22/24/25/26/27/28/29
J
= 85°C). As part of this qualification procedure, the
600
450
300
150
0
30
Figure 51. Flash/EE Memory Data Retention
40
JUNCTION TEMPERATURE (°C)
55
70
85
2
C.
100
125
135
150
2
C port.
J

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