ADUC7028 Analog Devices, ADUC7028 Datasheet - Page 87

• Manufacturer Part Number: ADUC7028
• Manufacturer: Analog Devices

Specifications of ADUC7028

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Flash (kbytes): 62Bytes
• Sram (bytes): 8192Bytes
• Gpio Pins: 40
• Adc # Channels: 8

HARDWARE DESIGN CONSIDERATIONS
POWER SUPPLIES
The ADuC7019/20/21/22/24/25/26/27/28/29 operational power
supply voltage range is 2.7 V to 3.6 V. Separate analog and
digital power supply pins (AV
AV
present on the system IOV
also operate with split supplies; that is, it can use different
voltage levels for each supply. For example, the system can be
designed to operate with an IOV
whereas the AV
split supply configuration is shown in Figure 75.
As an alternative to providing two separate power supplies, the
user can reduce noise on AV
and/or ferrite bead between AV
AV
shown in Figure 76. With this configuration, other analog circuitry
(such as op amps and voltage reference) can be powered from
the AV
Note that in both Figure 75 and Figure 76, a large value (10 μF)
reservoir capacitor sits on IOV
sits on AV
located at each AV
design practice, be sure to include all of these capacitors and ensure
that the smaller capacitors are close to each AV
lengths as short as possible. Connect the ground terminal of
each of these capacitors directly to the underlying ground plane.
DD
DD
DIGITAL SUPPLY
+
–
to be kept relatively free of noisy digital signals often
separately to ground. An example of this configuration is
DIGITAL
SUPPLY
10µF
+
–
DD
0.1µF
supply line as well.
DD
0.1µF
. In addition, local small-value (0.1 μF) capacitors are
Figure 76. External Single Supply Connections
Figure 75. External Dual Supply Connections
10µF
DD
26
54
25
53
DD
level can be at 3 V or vice versa. A typical
IOV
IOGND
26
54
25
53
and IOV
ADuC7026
DD
IOV
IOGND
ADuC7026
DD
DD
DACGND
REFGND
DACV
GND
DD
BEAD
line. In this mode, the part can
AGND
DD
DD
DD
AV
DD
DACGND
REFGND
by placing a small series resistor
DACV
GND
REF
DD
DD
DD
, and a separate 10 μF capacitor
pin of the chip. As per standard
and IOV
and IOV
AGND
AV
REF
voltage level of 3.3 V
73
74
75
70
71
67
8
DD
DD
73
74
75
70
71
67
8
1.6Ω
DD
DD
, respectively) allow
and then decoupling
10µF
DD
10µF
pin with trace
ANALOG
SUPPLY
0.1µF
+
–
0.1µF
Rev. D | Page 87 of 96
Finally, note that the analog and digital ground pins on the
ADuC7019/20/21/22/24/25/26/27/28/29 must be referenced to
the same system ground reference point at all times.
IOV
The IOV
is the supply source for the internal oscillator and PLL circuits.
When the internal PLL loses lock, the clock source is removed
by a gating circuit from the CPU, and the ARM7TDMI core
stops executing code until the PLL regains lock. This feature
ensures that no flash interface timings or ARM7TDMI timings
are violated.
Typically, frequency noise greater than 50 kHz and 50 mV p-p
on top of the supply causes the core to stop working.
If decoupling values recommended in the Power Supplies
section do not sufficiently dampen all noise sources below
50 mV on IOV
recommended.
Linear Voltage Regulator
Each ADuC7019/20/21/22/24/25/26/27/28/29 requires a single
3.3 V supply, but the core logic requires a 2.6 V supply. An on-
chip linear regulator generates the 2.6 V from IOV
core logic. The LV
An external compensation capacitor of 0.47 μF must be
connected between LV
these pins) to act as a tank of charge as shown in Figure 78.
The LV
recommended to use excellent power supply decoupling on
IOV
chip voltage regulator.
ADuC7019/20/21/22/24/25/26/27/28/29
DD
DD
Supply Sensitivity
to help improve line regulation performance of the on-
DD
DIGITAL
SUPPLY
DD
pin should not be used for any other chip. It is also
supply is sensitive to high frequency noise because it
Figure 77. Recommended IOV
Figure 78. Voltage Regulator Connections
DD
0.47μF
+
–
, a filter such as the one shown in Figure 77 is
DD
1µH
10µF
pin is the 2.6 V supply for the core logic.
DD
0.1µF
and DGND (as close as possible to
27
28
LV
DGND
ADuC7026
DD
26
54
25
53
IOV
IOGND
DD
ADuC7026
DD
Supply Filter
DD
for the