ADUC7020 Analog Devices, ADUC7020 Datasheet - Page 59

• Manufacturer Part Number: ADUC7020
• Manufacturer: Analog Devices

Specifications of ADUC7020

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 14
• Adc # Channels: 5

The PWMDAT1 register is a 10-bit register with a maximum
value of 0x3FF (= 1023), which corresponds to a maximum
programmed dead time of
for a core clock of 41.78 MHz.
The dead time can be programmed to be zero by writing 0 to
the PWMDAT1 register.
PWM Operating Mode (PWMCON and PWMSTA MMRs)
As discussed in the 3-Phase PWM section, the PWM controller
of the ADuC7019/20/21/22/24/25/26/27/28/29 can operate in
two distinct modes: single update mode and double update
mode. The operating mode of the PWM controller is
determined by the state of Bit 2 of the PWMCON register.
If this bit is cleared, the PWM operates in the single update
mode. Setting Bit 2 places the PWM in the double update
mode. The default operating mode is single update mode.
In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks the
start of a new PWM cycle and is used to latch new values from
the PWM configuration registers (PWMDAT0 and PWMDAT1)
and the PWM duty cycle registers (PWMCH0, PWMCH1, and
PWMCH2) into the 3-phase timing unit. In addition, the
PWMEN register is latched into the output control unit on the
rising edge of the PWMSYNC pulse. In effect, this means that
the characteristics and resulting duty cycles of the PWM signals
can be updated only once per PWM period at the start of each
cycle. The result is symmetrical PWM patterns about the
midpoint of the switching period.
In double update mode, there is an additional PWMSYNC
pulse produced at the midpoint of each PWM period. The
rising edge of this new PWMSYNC pulse is again used to latch
new values of the PWM configuration registers, duty cycle
registers, and the PWMEN register. As a result, it is possible to
alter both the characteristics (switching frequency and dead
time) as well as the output duty cycles at the midpoint of each
PWM cycle. Consequently, it is also possible to produce PWM
switching patterns that are no longer symmetrical about the
midpoint of the period (asymmetrical PWM patterns). In
double update mode, it could be necessary to know whether
operation at any point in time is in either the first half or the
second half of the PWM cycle. This information is provided by
Bit 0 of the PWMSTA register, which is cleared during operation
in the first half of each PWM period (between the rising edge of
the original PWMSYNC pulse and the rising edge of the new
PWMSYNC pulse introduced in double update mode). Bit 0 of
the PWMSTA register is set during operation in the second half
of each PWM period. This status bit allows the user to make a
determination of the particular half cycle during implementation
of the PWMSYNC interrupt service routine, if required.
t
D(max)
= 1023 × 2 × t
CORE
= 1023 × 2 × 24 ×10
–9
= 48.97 μs
Rev. D | Page 59 of 96
The advantage of double update mode is that lower harmonic
voltages can be produced by the PWM process, and faster
control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Because new duty cycle values
must be computed in each PWMSYNC interrupt service
routine, there is a larger computational burden on the ARM
core in double update mode.
PWM Duty Cycles (PWMCH0, PWMCH1, and
PWMCH2 MMRs)
The duty cycles of the six PWM output signals on Pin PWM0
to Pin PWM2
cycle registers, PWMCH0, PWMCH1, and PWMCH2. The
duty cycle registers are programmed in integer counts of the
fundamental time unit, t
the high-side PWM signal produced by the 3-phase timing unit
over half the PWM period. The switching signals produced by
the 3-phase timing unit are also adjusted to incorporate the
programmed dead time value in the PWMDAT1 register. The
3-phase timing unit produces active high signals so that a high
level corresponds to a command to turn on the associated
power device.
Figure 59 shows a typical pair of PWM outputs (in this case, 0H
and 0L) from the timing unit in single update mode. All
illustrated time values indicate the integer value in the
associated register and can be converted to time by simply
multiplying by the fundamental time increment, t
the switching patterns are perfectly symmetrical about the
midpoint of the switching period in this mode because the same
values of PWMCH0, PWMDAT0, and PWMDAT1 are used to
define the signals in both half cycles of the period.
Figure 59 also demonstrates how the programmed duty cycles
are adjusted to incorporate the desired dead time into the
resulting pair of PWM signals. The dead time is incorporated
by moving the switching instants of both PWM signals (0H and
0L) away from the instant set by the PWMCH0 register.
ADuC7019/20/21/22/24/25/26/27/28/29
PWMSTA (0)
PWMSYNC
–PWMDAT0 ÷ 2
Figure 59. Typical PWM Outputs of the 3-Phase Timing Unit
0H
0L
PWMCH0
2 × PWMDAT1
L
are controlled by the three 16-bit read/write duty
PWMDAT0
(Single Update Mode)
0
CORE
. They define the desired on time of
+PWMDAT0 ÷ 2
PWMDAT0
PWMDAT2 + 1
0
2 × PWMDAT1
PWMCH0
CORE
–PWMDAT0 ÷ 2
. Note that
H