DS2167Q Maxim Integrated Products, DS2167Q Datasheet - Page 5

IC PROC ADPCM 16/24/32K 28-PLCC

DS2167Q

Manufacturer Part Number
DS2167Q
Description
IC PROC ADPCM 16/24/32K 28-PLCC
Manufacturer
Maxim Integrated Products
Type
ADPCM Processorr
Datasheet

Specifications of DS2167Q

Mounting Type
Surface Mount
Package / Case
28-LCC, 28-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Applications
-

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CODEC/FILTER HARDWARE MODE INTERCONNECT Figure 2
NOTE:
Suggested Codec/Filters
SOFTWARE MODE
Tying SPS high enabled the software mode. In this
mode, a host microcontroller writes configuration data
to the DS2167/DS2168 serial port via inputs SCLK, SDI,
and CS. Independent control and timeslot registers es-
tablish operating characteristics for the X-side and Y-
side PCM interfaces.
ADDRESS/COMMAND BYTE
In the software mode, the address/command byte is the
first byte written to the serial port; it identifies which of 64
possible ADPCM processors sharing the port wiring is
to be updated. Address data must match that at inputs
TRANSMIT FRAME SYNC
TRANSMIT DATA CLOCK
RECEIVE DATA CLOCK
RECEIVE FRAME SYNC
INTERFACE
INTERFACE
TP305X
ETC505X
MC1455XX
TCM29CXX
HD44238C
*other generic Codec/Filter devices can be substituted.
TRANSMIT
RECEIVE
ANALOG
ANALOG
-5.0 V
National Semiconductor
SGS–Thomson Microelectronics
Motorola
Texas Instruments
Hitachi
VCC
VBB
GNDA
TSX
VFXI+
VFSI-
GSX
VFRO
MCLK/PDN
CLKSEL
MCLKX
BCLKX
BCLK/
FSR
FSX
DR
DX
A0–A5. If no match occurs, the device ignores the fol-
lowing configuration data. If an address match occurs,
the next three bytes written are accepted as control, in-
put and output timeslot data. Bit ACB.6 determines
which side (X or Y) of the device is to be updated.
CONTROL REGISTER
The control register establishes idle, algorithm reset,
bypass, data format and channel coding for the selected
PCM interface.
The X and Y side PCM interfaces may be independently
disabled (output tri-stated) via IPD; when IPD is set for
RST
SCLK
XIN
FSX
CLKX
YOUT
FSY
CLKY
SPS
TM0
TM1
VSS
POWER ON RESET
(DS1231)
XOUT
MCLK
VDD
YIN
SDI
CS
A5
A2
A3
A4
A1
A0
TP3054 (µ-LAW)
TP3057 (µ-LAW)
TRANSMIT DATA
RECEIVE DATA
POWER DOWN
ACTIVE
10 MHz CLOCK
DS2167/DS2168
022698 5/15

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