LPC1759FBD80 NXP Semiconductors, LPC1759FBD80 Datasheet - Page 32

The LPC1759 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz

LPC1759FBD80

Manufacturer Part Number
LPC1759FBD80
Description
The LPC1759 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
LPC1759_58_56_54_52_51
Product data sheet
7.29.5.3 Power-down mode
7.29.5.4 Deep power-down mode
7.29.5.5 Wakeup interrupt controller
7.29.6 Peripheral power control
7.29.7 Power domains
On wake-up from Deep-sleep mode, the code execution and peripherals activities will
resume after 4 cycles expire if the IRC was used before entering Deep-sleep mode. If the
main external oscillator was used, the code execution will resume when 4096 cycles
expire. PLL and clock dividers need to be reconfigured accordingly.
Power-down mode does everything that Deep-sleep mode does, but also turns off the
power to the IRC oscillator and the flash memory. This saves more power but requires
waiting for resumption of flash operation before execution of code or data access in the
flash memory can be accomplished.
On the wake-up of Power-down mode, if the IRC was used before entering Power-down
mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire before the code
execution can then be resumed if the code was running from SRAM. In the meantime, the
flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 s flash start-up
time. When it times out, access to the flash will be allowed. Users need to reconfigure the
PLL and clock dividers accordingly.
The Deep power-down mode can only be entered from the RTC block. In Deep
power-down mode, power is shut off to the entire chip with the exception of the RTC
module and the RESET pin.
The LPC1759/58/56/54/52/51 can wake up from Deep power-down mode via the RESET
pin or an alarm match event of the RTC.
The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from any
enabled priority interrupt that can occur while the clocks are stopped in Deep sleep,
Power-down, and Deep power-down modes.
The Wakeup Interrupt Controller (WIC) works in connection with the Nested Vectored
Interrupt Controller (NVIC). When the CPU enters Deep sleep, Power-down, or Deep
power-down mode, the NVIC sends a mask of the current interrupt situation to the
WIC.This mask includes all of the interrupts that are both enabled and of sufficient priority
to be serviced immediately. With this information, the WIC simply notices when one of the
interrupts has occurred and then it wakes up the CPU.
The Wakeup Interrupt Controller (WIC) eliminates the need to periodically wake up the
CPU and poll the interrupts resulting in additional power savings.
A power control for peripherals feature allows individual peripherals to be turned off if they
are not needed in the application, resulting in additional power savings.
The LPC1759/58/56/54/52/51 provide two independent power domains that allow the bulk
of the device to have power removed while maintaining operation of the RTC and the
backup Registers.
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 29 March 2011
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2011. All rights reserved.
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