LPC1759FBD80 NXP Semiconductors, LPC1759FBD80 Datasheet - Page 50

The LPC1759 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz

LPC1759FBD80

Manufacturer Part Number
LPC1759FBD80
Description
The LPC1759 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
LPC1759_58_56_54_52_51
Product data sheet
11.5 I
Table 12.
T
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
Symbol
f
t
t
t
t
t
2
SCL
f
LOW
HIGH
HD;DAT
SU;DAT
amb
C-bus
See the I
Parameters are valid over operating temperature range unless otherwise specified.
t
and the acknowledge.
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
V
C
The maximum t
output stage t
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
The maximum t
the maximum of t
maximum must only be met if the device does not stretch the LOW period (t
clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
t
transmission and the acknowledge.
HD;DAT
SU;DAT
=
IH
b
= total capacitance of one bus line in pF.
(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
40
is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
Dynamic characteristic: I
C to +85
2
C-bus specification UM10204 for details.
Parameter
SCL clock
frequency
fall time
LOW period of
the SCL clock
HIGH period of
the SCL clock
data hold time
data set-up
time
f
All information provided in this document is subject to legal disclaimers.
is specified at 250 ns. This allows series protection resistors to be connected in between the
HD;DAT
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
VD;DAT
C.
could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than
[2]
Rev. 7 — 29 March 2011
or t
VD;ACK
[4][5][6][7]
[3][4][8]
[9]
by a transition time (see the I
2
C-bus pins
Conditions
Standard-mode
Fast-mode
of both SDA and
SCL signals
Standard-mode
Fast-mode
Standard-mode
Fast-mode
Standard-mode
Fast-mode
Standard-mode
Fast-mode
Standard-mode
Fast-mode
LPC1759/58/56/54/52/51
[1]
32-bit ARM Cortex-M3 microcontroller
2
C-bus specification UM10204). This
Min
0
0
-
20 + 0.1  C
4.7
1.3
4.0
0.6
0
0
250
100
LOW
b
) of the SCL signal. If the
© NXP B.V. 2011. All rights reserved.
Max
100
400
300
300
-
-
-
-
-
-
-
-
f
.
Unit
kHz
kHz
ns
ns
s
s
s
s
s
s
ns
ns
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