LPC1759FBD80 NXP Semiconductors, LPC1759FBD80 Datasheet - Page 66

The LPC1759 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz

LPC1759FBD80

Manufacturer Part Number
LPC1759FBD80
Description
The LPC1759 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
LPC1759_58_56_54_52_51
Product data sheet
14.4 Standard I/O pin configuration
order to keep the noise coupled in via the PCB as small as possible. Also parasitics
should stay as small as possible. Values of C
accordingly to the increase in parasitics of the PCB layout.
Figure 34
The default configuration for standard I/O pins is input with pull-up enabled. The weak
MOS devices provide a drive capability equivalent to pull-up and pull-down resistors.
Fig 34. Standard I/O pin configuration with analog input
as digital output
as analog input
as digital input
pin configured
pin configured
pin configured
Digital output driver: Open-drain mode enabled/disabled
Digital input: Pull-up enabled/disabled
Digital input: Pull-down enabled/disabled
Digital input: Repeater mode enabled/disabled
Analog input
driver
shows the possible pin modes for standard I/O pins with analog input function:
All information provided in this document is subject to legal disclaimers.
open-drain enable
repeater mode
output enable
analog input
data output
Rev. 7 — 29 March 2011
data input
enable
pull-down enable
LPC1759/58/56/54/52/51
pull-up enable
select analog input
x1
and C
32-bit ARM Cortex-M3 microcontroller
x2
should be chosen smaller
V
V
DD
DD
strong
pull-up
strong
pull-down
weak
pull-up
weak
pull-down
© NXP B.V. 2011. All rights reserved.
V
ESD
DD
ESD
V
SS
002aaf272
66 of 74
PIN

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