LPC1850FET256 NXP Semiconductors, LPC1850FET256 Datasheet - Page 58
LPC1850FET256
Manufacturer Part Number
LPC1850FET256
Description
The LPC1850FET256 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 200 kB of SRAM, and advanced peripherals including Ethernet, High Speed USB 2
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1810FBD144.pdf
(157 pages)
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Table 3.
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See
LPC1850_30_20_10
Preliminary data sheet
Symbol
PF_2
PF_3
PF_4
Pin description
D11
E10
D10
-
-
x
…continued
-
-
H4
170 -
168 -
172 120 83
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 15 December 2011
-
-
[3]
[3]
[3]
I; PU -
I; PU -
O;
PU
O
I/O SSP0_MISO — Master In Slave Out for SSP0.
-
I/O GPIO7[17] — General purpose digital input/output
-
-
-
I
I/O SSP0_MOSI — Master Out Slave in for SSP0.
-
I/O GPIO7[18] — General purpose digital input/output
-
-
-
I/O SSP1_SCK — Serial clock for SSP1.
I
O
-
-
-
O
I/O I2S0_RX_SCK — I
Description
R — Function reserved.
U3_TXD — Transmitter output for USART3.
R — Function reserved.
pin.
R — Function reserved.
R — Function reserved.
R — Function reserved.
R — Function reserved.
U3_RXD — Receiver input for USART3.
R — Function reserved.
pin.
R — Function reserved.
R — Function reserved.
R — Function reserved.
GP_CLKIN — General purpose clock input to the
CGU.
TRACECLK — Trace clock.
R — Function reserved.
R — Function reserved.
R — Function reserved.
I2S0_TX_MCLK — I
the master and received by the slave. Corresponds
to the signal SCK in the I
Table
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
2.
2
S receive clock. It is driven by
2
S transmit master clock.
2
S-bus specification.
© NXP B.V. 2011. All rights reserved.
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