LH75401_LH75411_N NXP Semiconductors, LH75401_LH75411_N Datasheet - Page 26

• Manufacturer Part Number: LH75401_LH75411_N
• Description: The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip (SoC) devices
• Manufacturer: NXP Semiconductors

LH75401/LH75411
Static Random Access Memory Controller
of Static Random Access Memory (SRAM) organized
into two 16 kB blocks:
• 16 kB of TCM 0 Wait State SRAM is available to the
• 16 kB of internal SRAM is available as an AHB slave
and internal SRAMs are 16 kB each in size. Any
access beyond the first 16 kB is mapped to the lower
16 kB, but does not cause a data or prefetch abort.
Static Memory Controller (SMC)
AHB slave peripheral that provides the interface
between the LH75401/LH75411 microcontrollers and
external memory devices.
SMC FEATURES
• Provides four banks of external memory, each with a
0xFFFDC000 - 0xFFFDCFFF GPIO3
0xFFFDD000 - 0xFFFDDFFF GPIO2
0xFFFC7000 - 0xFFFDAFFF Reserved
0xFFFDB000 - 0xFFFDBFFF GPIO4
0xFFFDE000 - 0xFFFDEFFF GPIO1
0xFFFDF000 - 0xFFFDFFFF GPIO0
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0xFFFC0000 - 0xFFFC0FFF UART0 (16550)
0xFFFC1000 - 0xFFFC1FFF UART1 (16550)
0xFFFC2000 - 0xFFFC2FFF UART2 (82510)
0xFFFC3000 - 0xFFFC3FFF Analog-to-Digital Converter
0xFFFC4000 - 0xFFFC4FFF Timer Module
0xFFFC5000 - 0xFFFC5FFF
0xFFFC6000 - 0xFFFC6FFF Synchronous Serial Port
0xFFFE0000 - 0xFFFE0FFF Real Time Clock
0xFFFE1000 - 0xFFFE1FFF DMAC
0xFFFE2000 - 0xFFFE2FFF
0xFFFE3000 - 0xFFFE3FFF Watchdog Timer
0xFFFE4000 - 0xFFFE4FFF Advanced LCD Interface
0xFFFE5000 - 0xFFFE5FFF I/O Configuration Peripheral
0xFFFE6000 - 0xFFFEFFFF Reserved
processor as an ARM7TDMI-S bus slave.
and accessible via processor, DMAC, and LCDC.
maximum size of 16 MB.
The LH75401/LH75411 microcontrollers have 32 kB
Each memory segment is 512 MB, though the TCM
The Static Memory Controller (SMC) is an AMBA
Table 8. APB Peripheral Register Mapping
ADDRESS RANGE
CAN (LH75401)
Reserved (LH75411)
Reset Clock and Power
Controller
DEVICE
NXP Semiconductors
Rev. 01 — 16 July 2007
• Supports
• Supports external bus and external device widths of
• Supports Asynchronous Burst Mode read access for
• Supports indefinite extended wait states via an
• Supports varied bus turnaround cycles (1 to 16)
Direct Memory Access Controller (DMAC)
requirements for the DMA-capable peripherals listed in
Table 9.
APB slave port for programming of its registers and an
AHB port for data transfers.
DMAC FEATURES
• Four data streams that can be used to service:
• Three transfer modes:
• Built-in data stream arbiter
• Seven programmable registers for each stream
• Ability for each stream to indicate a transfer error via
• 16-word First-In, First Out (FIFO) array, with pack
• APB slave port allows the ARM core to program
• AHB port for data transfers.
UART1RX (highest priority)
UART1TX
UART0RX/External Request (DREQ)
UART0TX (lowest priority)
Random Access Memory (RAM), Read Only
Memory (ROM), Flash, and burst ROM
8 and 16 bits
Burst Mode ROM devices, with up to 32 independent
wait states for read and write accesses
external hardware pin (nWAIT)
between a read and write operation
an interrupt
and unpack logic to handle all input/output combina-
tions of byte, half-word, and word transfers
DMAC registers
One central DMAC services all peripheral DMA
The DMA is controlled by the system clock. It has an
– Four peripheral data streams (peripheral-to-
– Three peripheral data streams and one memory-
– Memory to Memory (selectable on Stream3)
– Peripheral to Memory (all streams)
– Memory to Peripheral (all streams).
memory or memory-to-peripheral)
to-memory data stream.
DMA REQUEST SOURCE
Table 9. DMAC Stream Assignments
memory-mapped
Preliminary data sheet
devices,
System-on-Chip
DMA STREAM
Stream0
Stream1
Stream2
Stream3
including