LPC2212_2214 NXP Semiconductors, LPC2212_2214 Datasheet - Page 4
LPC2212_2214
Manufacturer Part Number
LPC2212_2214
Description
The LPC2212/2214 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulationand embedded trace support, together with 128/256 kB of embedded high-speed flashmemory
Manufacturer
NXP Semiconductors
Datasheet
1.LPC2212_2214.pdf
(47 pages)
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NXP Semiconductors
4. Block diagram
LPC2212_2214
Product data sheet
Fig 1. Block diagram
PWM[6:1]
4 × CAP0
4 × CAP1
EINT[3:0]
4 × MAT0
4 × MAT1
AIN[3:0]
AIN[7:4]
P0[30:27],
P1[31:16],
(1) Shared with GPIO.
(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(3) SSP interface and high-speed GPIO are available on LPC2212/01 and LPC2214/01 only.
P0[25:0]
P2[31:0]
P3[31:0]
P1[1:0]
P0, P1
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
CONTROLLER
INTERNAL
SRAM
SRAM
16 kB
48 PINS TOTAL
ARM7 LOCAL BUS
HIGH-SPEED
SYSTEM CONTROL
REAL-TIME CLOCK
LPC2212
LPC2214
TIMER 0/TIMER 1
A/D CONVERTER
GPI/O
PURPOSE I/O
INTERRUPTS
EXTERNAL
CAPTURE/
COMPARE
GENERAL
PWM0
(3)
CONTROLLER
128/256 kB
INTERNAL
FLASH
FLASH
All information provided in this document is subject to legal disclaimers.
TRST
(2)
TMS
ARM7TDMI-S
TEST/DEBUG
AHB BRIDGE
INTERFACE
Rev. 5 — 14 June 2011
(2)
TCK
AHB TO APB
BRIDGE
(2)
TDI
TDO
(2)
RTCK
(2)
AMBA Advanced High-performance
DIVIDER
APB
Bus (AHB)
system
Single-chip 16/32-bit ARM microcontrollers
clock
EXTERNAL MEMORY
PLL
SPI1/SSP
I
2
CONTROLLER
UART0/UART1
C-BUS SERIAL
SPI0 SERIAL
WATCHDOG
INTERFACE
INTERFACE
INTERFACE
TIMER
XTAL1
(3)
CONTROLLER
INTERRUPT
FUNCTIONS
VECTORED
DECODER
SERIAL
SYSTEM
LPC2212/2214
XTAL2
AHB
002aad181
RESET
© NXP B.V. 2011. All rights reserved.
V
V
V
DD(3V3)
DD(1V8)
SS
CS[3:0]
A[23:0]
BLS[3:0]
OE, WE
D[31:0]
SCL
SDA
SCK1
MOSI1
MISO1
SSEL1
SCK0
MOSI0
MISO0
SSEL0
TXD[1:0]
RXD[1:0]
DSR1
RTS1
DCD1
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
, DTR1
(1)
, CTS1
, RI1
(1)
(1)
(1)
(1)
4 of 47
(1)
(1)
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