LPC2420_60 NXP Semiconductors, LPC2420_60 Datasheet - Page 44



Manufacturer Part Number
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
NXP Semiconductors
NXP Semiconductors
Product data sheet Deep power-down mode Power domains
Deep power-down mode is similar to the Power-down mode, but now the on-chip
regulator that supplies power to the internal logic is also shut off. This produces the lowest
possible power consumption without removing power from the entire chip. Since the Deep
power-down mode shuts down the on-chip logic power supply, there is no register or
memory retention, and resumption of operation involves the same activities as a full chip
If power is supplied to the LPC2420/2460 during Deep power-down mode, wake-up can
be caused by the RTC Alarm interrupt or by external Reset.
While in Deep power-down mode, external device power may be removed. In this case,
the LPC2420/2460 will start up when external power is restored.
Essential data may be retained through Deep power-down mode (or through complete
powering off of the chip) by storing data in the Battery RAM, as long as the external power
to the VBAT pin is maintained.
The LPC2420/2460 provides two independent power domains that allow the bulk of the
device to have power removed while maintaining operation of the RTC and the Battery
On the LPC2420/2460, I/O pads are powered by the 3.3 V (V
the CPU and most of the peripherals.
Although both the I/O pad ring and the core require a 3.3 V supply, different powering
schemes can be used depending on the actual application requirements.
The first option assumes that power consumption is not a concern and the design ties the
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (V
a dedicated 3.3 V supply for the CPU (V
converter powered independently from the I/O pad ring enables shutting down of the I/O
pad power supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that may be used by external hardware to restore chip power
and resume operation.
and V
pins power the on-chip DC-to-DC converter which in turn provides power to
All information provided in this document is subject to legal disclaimers.
Rev. 6.1 — 22 September 2011
pins together. This approach requires only one 3.3 V power
Flashless 16-bit/32-bit microcontroller
). Having the on-chip DC-DC
) pins, while the
© NXP B.V. 2011. All rights reserved.
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) and

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