LPC2420_60 NXP Semiconductors, LPC2420_60 Datasheet - Page 45



Manufacturer Part Number
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
NXP Semiconductors
NXP Semiconductors
Product data sheet
7.25.1 Reset
7.25.2 Boot process
7.25.3 Brownout detection
7.25 System control
Reset has four sources on the LPC2420/2460: the RESET pin, the Watchdog reset,
power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains
a usable level, starts the wake-up timer (see description in
timer”), causing reset to remain asserted until the external Reset is de-asserted, the
oscillator is running, and a fixed number of clocks have passed.
Once the internal reset is removed, all of the processor and peripheral registers have
been initialized to predetermined values and the LPC2420/2460 continues with booting
from an external static memory.
The processor always boots from the off-chip static memory bank 1, executing code from
address 0x8100 0000 (see
the boot process initiated by POR, the boot pins P3[15]/D15 and P3[14]/D14 are sampled,
and the external memory banks 0 and 1 are configured with the same data bus width. The
data bus width is determined by the setting of the two boot pins. Unused address pins are
configured as GPIO. See
an example of address and data bus interfacing.
Remark: After POR, the address ranges of chip select 1 and chip select 0 are swapped.
The user code residing in the external boot memory must be linked to execute from
address location 0x8000 0000.
When booting from external memory, the interrupt vectors are mapped to the bottom of
the external memory. Once booting is over, the application must map interrupt vectors to
the proper domain.
The LPC2420/2460 includes 2-stage monitoring of the voltage on the V
If this voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored
Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable
Register in the VIC in order to cause a CPU interrupt; if not, software can monitor the
signal by reading a dedicated status register.
The second stage of low-voltage detection asserts a BOD Reset and generates a Reset (if
this reset source is enabled in software) to inactivate the LPC2420/2460 when the voltage
on the V
below 1 V, at which point the power-on reset circuitry maintains the overall Reset.
Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
All information provided in this document is subject to legal disclaimers.
Rev. 6.1 — 22 September 2011
pins falls below 2.65 V. The BOD circuit maintains this reset down
Section 14.1 “Suggested boot memory interface solutions”
Table 5 “LPC2420/2460 memory usage and
Flashless 16-bit/32-bit microcontroller
Section 7.24.3 “Wake-up
© NXP B.V. 2011. All rights reserved.
details”). During
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