LPC3130_3131 NXP Semiconductors, LPC3130_3131 Datasheet - Page 21

• Manufacturer Part Number: LPC3130_3131
• Description: The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC3130_3131_1
Preliminary data sheet
6.13 Multi-layer AHB
The following blocks can generate interrupts:
The multi-layer AHB is an interconnection scheme based on the AHB protocol that
enables parallel access paths between multiple masters and slaves in a system.
Multiple masters can have access to different slaves at the same time.
Figure 5
AHB masters and slaves are numbered according to their AHB port number.
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Level interrupt support.
NAND flash controller
USB 2.0 high-speed OTG
Event router
10-bit ADC
UART
LCD
MCI
SPI
I2C0 and I2C1 controllers
Timer0, Timer1, Timer2, and Timer3
I
I
DMA
2
2
S transmit: I2STX_0 and I2STX_1
S receive: I2SRX_0 and I2SRX_1
gives an overview of the multi-layer AHB configuration in the LPC3130/3131.
Rev. 1 — 9 February 2009
Low-cost, low-power ARM926EJ-S microcontrollers
LPC3130/3131
© NXP B.V. 2009. All rights reserved.
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