LPC3130_3131 NXP Semiconductors, LPC3130_3131 Datasheet - Page 3

The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2

LPC3130_3131

Manufacturer Part Number
LPC3130_3131
Description
The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
4. Block diagram
LPC3130_3131_1
Preliminary data sheet
Fig 1.
CONTROLLLER
(1)
INTERRUPT
LPC3130/3131 block diagram
SD/SDIO
SYSTEM CONTROL
RANDOM NUMBER
LPC3131 only
MPMC
EVENT ROUTER
APB slave group 0
MCI
GENERATOR
IOCONFIG
10-bit ADC
WDT
CGU
slave
slave
slave
slave
TIMER 0/1/2/3
ARM926EJ-S
APB slave group 1
TEST/DEBUG
PWM
INTERFACE
I2C0
I2C1
interface
BRIDGE 0
master
JTAG
AHB TO
ASYNC
APB
slave
master
BRIDGE 1
MULTILAYER AHB MATRIX
AHB TO
ASYNC
APB
Rev. 1 — 9 February 2009
CONTROLLER
slave
DMA
BRIDGE 2
AHB TO
ASYNC
master
APB
LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
slave
APB slave group 2
HIGH-SPEED
USB 2.0
BRIDGE 3
master
AHB TO
ASYNC
OTG
APB
UART
LCD
PCM
SPI
slave
APB slave group 3
slave
BRIDGE 4
AHB TO
SYNC
I2S0/1
APB
slave
slave
slave
slave
slave
APB slave group 4
LPC3130/3131
NAND REGISTERS
DMA REGISTERS
NAND CONTROLLER
96 kB ISRAM1
96 kB ISRAM0
BUFFER
ROM
© NXP B.V. 2009. All rights reserved.
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