LPC3130_3131 NXP Semiconductors, LPC3130_3131 Datasheet - Page 30

• Manufacturer Part Number: LPC3130_3131
• Description: The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC3130_3131_1
Preliminary data sheet
6.25 I
6.26 LCD/NAND flash/SDRAM multiplexing
The LPC3130/3131 contains two I
This module has the following features:
The LPC3130/3131 contains a rich set of specialized hardware interfaces but the TFBGA
package does not contain enough pins to allow use of all signals of all interfaces
simultaneously. Therefore a pin-multiplexing scheme is created, which allows the
selection of the right interface for the application.
Pin multiplexing is enabled between the following interfaces:
The pin interface multiplexing is subdivided into five categories: storage, video, audio,
NAND flash, and UART related pin multiplexing. Each category supports several modes,
which can be selected by programming the corresponding registers in the SysCReg.
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C-bus master/slave interface
I
open-drain pins. This interface supports functions described in the I
specification for speeds up to 400 kHz. This includes multi-master operation and
allows powering off this device in a working system while leaving the I
functional.
I
single-master I
also do not support multi-master I
Supports normal mode (100 kHz SCL).
Fast mode (400 kHz SCL with 24 MHz APB clock; 325 kHz with12 MHz APB clock;
175 kHz with 6 MHz APB clock).
Interrupt support.
Supports DMA transfers (single).
Four modes of operation:
– Master transmitter
– Master receiver
– Slave transmitter
– Slave receiver
between the dedicated LCD interface and the external bus interface.
between the NAND flash controller and the memory card interface.
between UART and SPI.
between I2STX_0 output and the PCM interface.
2
2
C-bus interface 0 (I2C0): I2C0 is a standard I
C-bus interface 1 (I2C1): I2C1 uses standard I/O pins and is intended for use with a
2
C-bus and does not support powering off of this device. Standard I/Os
Rev. 1 — 9 February 2009
2
Low-cost, low-power ARM926EJ-S microcontrollers
C master/slave interfaces.
2
C implementations.
2
C-compliant bus interface with
LPC3130/3131
© NXP B.V. 2009. All rights reserved.
2
C-bus
2
C-bus
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