LPC3130_3131 NXP Semiconductors, LPC3130_3131 Datasheet - Page 40

The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2

LPC3130_3131

Manufacturer Part Number
LPC3130_3131
Description
The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
Table 13.
V
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
LPC3130_3131_1
Preliminary data sheet
Symbol
V
C
N
E
E
E
E
E
V
V
R
DD(ADC)
IA
D
L(adj)
O
G
T
err(O)
err(FS)
ia
res(ADC)
vsi
On pin ADC10B_GNDA.
Conditions: V
The ADC is monotonic, there are no missing codes.
The differential linearity error (E
The integral non-linearity (E
appropriate adjustment of gain and offset errors. See
The offset error (E
ideal curve. See
The gain error (E
error, and the straight line which fits the ideal transfer curve. See
The absolute error (E
and the ideal transfer curve. See
See
Figure
= 2.7 V to 3.6 V; T
ADC static characteristics
Parameter
analog input voltage
analog input capacitance
ADC resolution
differential linearity error
integral non-linearity
offset error
gain error
absolute error
offset error voltage
full-scale error voltage
voltage source interface
resistance
11.
SSA
Figure
G
= 0 V on pin ADC10B_GNDA, V
O
) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
T
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC
10.
amb
L(adj)
= 40 C to +85 C unless otherwise specified; ADC frequency <tbd>.
D
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
) is the difference between the actual step width and the ideal step width. See
Figure
10.
Conditions
DD(ADC)
Rev. 1 — 9 February 2009
Figure
= 3.3 V.
10.
Figure
Low-cost, low-power ARM926EJ-S microcontrollers
10.
[2][3][4]
[2][5]
[2][6]
[2][7]
[2][8]
[9]
Min
0
-
2
-
-
-
-
-
<tbd>
-
[1]
20
Typ
-
-
-
-
-
-
-
-
-
-
-
LPC3130/3131
Max
V
<tbd>
10
<tbd>
<tbd>
<tbd>
+20
<tbd>
<tbd>
Figure
© NXP B.V. 2009. All rights reserved.
1
1
DD(ADC)
10.
Unit
V
pF
bit
LSB
LSB
LSB
%
LSB
mV
mV
k
40 of 68

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