LPC3130_3131 NXP Semiconductors, LPC3130_3131 Datasheet - Page 43

The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2

LPC3130_3131

Manufacturer Part Number
LPC3130_3131
Description
The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
9. Dynamic characteristics
LPC3130_3131_1
Preliminary data sheet
Fig 12. LCD timing (Intel 8080 mode)
mLCD_DB[15:0] (16 bit mode),
mLCD_DB[15:12] (4 bit mode)
mLCD_DB[15:0] (16 bit mode),
mLCD_DB[15:8] (8 bit mode),
mLCD_DB[15:12] (4 bit mode)
mLCD_DB[15:8] (8 bit mode),
9.1.1 Intel 8080 mode
9.1 LCD controller
mLCD_RW_WR,
Table 14.
C
[1]
Symbol
t
t
t
t
t
t
t
t
t
t
t
mLCD_E_RD
su(A)
h(A)
cy(a)
w(en)W
w(en)R
r
f
su(D)
h(D)
d(QV)
dis(Q)
L
mLCD_CSB
= 25 pF, T
mLCD_RS
Timing is determined by the LCD Interface Control Register fields: INVERT_CS = 1; MI = 0; PS = 0;
INVERT_E_RD = 0. See LPC3130/3131 user manual .
Dynamic characteristics: LCD controller in Intel 8080 mode
Parameter
address set-up time
address hold time
access cycle time
write enable pulse width
read enable pulse width
rise time
fall time
data input set-up time
data input hold time
data output valid delay time
data output disable time
amb
= 40 C to +85 C, unless otherwise specified; V
t
Rev. 1 — 9 February 2009
su(A)
t
f
t
d(QV)
t
w(en)R
Low-cost, low-power ARM926EJ-S microcontrollers
and t
t
su(D)
Conditions
w(en)W
t
cy(a)
t
r
t
h(D)
t
h(A)
t
dis(Q)
[1]
[1]
[1]
Min
-
-
-
-
-
2
2
<tbd>
<tbd>
-
-
LPC3130/3131
DD(IO)
Typ
1
2
5
2
2
-
-
-
-
2
1
= 1.8 V and 2.8 V (SUP8).
LCDCLK
LCDCLK
LCDCLK
LCDCLK
LCDCLK
LCDCLK
LCDCLK -
read access
write access
© NXP B.V. 2009. All rights reserved.
002aae207
Max Unit
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-
-
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5
5
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43 of 68
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