LPC3130_3131 NXP Semiconductors, LPC3130_3131 Datasheet - Page 59

The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2

LPC3130_3131

Manufacturer Part Number
LPC3130_3131
Description
The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
Table 25.
C
[1]
LPC3130_3131_1
Preliminary data sheet
Symbol
t
t
t
V
t
t
t
t
t
t
r
f
FRFM
FEOPT
FDEOP
JR1
JR2
EOPR1
EOPR2
Fig 27. I
L
CRS
= 50 pF; R
Characterized but not implemented as production test. Guaranteed by design.
SDA
SCL
Remark: Signals SDA and SCL correspond to pins I2C_SDAx and I2C_SCLx (x = 0, 1).
2
C-bus pins clock timing
Dynamic characteristics: USB pins (high-speed)
P
pu
= 1.5 k on D+ to V
9.9 USB interface
Parameter
rise time
fall time
differential rise and fall time
matching
output signal crossover voltage
source SE0 interval of EOP
source jitter for differential transition
to SE0 transition
receiver jitter to next transition
receiver jitter for paired transitions
EOP width at receiver
EOP width at receiver
t
BUF
S
t
HD;STA
t
LOW
DD(IO)
(SUP3), unless otherwise specified.
t
t
HD;STA
r
Rev. 1 — 9 February 2009
t
HIGH
Conditions
10 % to 90 %
10 % to 90 %
see
see
10 % to 90 %
must reject as
EOP; see
Figure 28
must accept as
EOP; see
Figure 28
t
r
/ t
Figure 28
Figure 28
f
Low-cost, low-power ARM926EJ-S microcontrollers
t
f
t
SU;DAT
S
t
[1]
[1]
SU;STA
Min
<tbd>
<tbd>
-
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
t
HD;STA
LPC3130/3131
Typ
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2009. All rights reserved.
Max
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
-
-
002aad985
t
SU;STO
P
59 of 68
Unit
ns
ns
%
V
ns
ns
ns
ns
ns
ns

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