XA-C3 NXP Semiconductors, XA-C3 Datasheet
XA-C3
Related parts for XA-C3
XA-C3 Summary of contents
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... XA-C3 XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-processor Preliminary specification Supersedes data of 1999 Dec 20 hilips Semiconductors INTEGRATED CIRCUITS 2000 Jan 25 ...
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... XA-C3 CAN AND CTL FEATURES ...
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... CTL/CAN Functionality of the XA-C3 ...
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... Background: XA Power–Down and Idle modes XA-C3 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Preliminary specification XA- ...
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... Figure 4. XA-C3 Simplified Block Diagram Figure 5 ...
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... Preliminary specification XA- ...
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... Message Objects that can 256 bytes each). LOGIC SYMBOL AND BLOCK DIAGRAM Refer to Figure 3 for the logic symbol for the XA-C3 and to Figure 4 for a simplified block diagram representation. UPGRADING XA-G3 DESIGNS TO CAN XA-G3 NC pins are XA-C3 CAN RxD and CAN TxD pins. ...
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... PXAC37KBA 0 to +70 PXAC37KFBD –40 to +85 PXAC37KFA –40 to +85 2000 Jan 25 Package Description Operating Frequency Low Profile PQFP [LQFP44] 32 PLCC [PLCC44] 32 Low Profile PQFP [LQFP44] 32 PLCC [PLCC44 Preliminary specification XA-C3 Drawing Number (MHz) SOT389–1 SOT187–2 SOT389–1 SOT187–2 ...
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... All active–low signals are indicated by a “/” symbol 2000 Jan 25 Figure 1. 44-pin PLCC package Pin P2.0 ; A12D8 25 P2.1 ; A13D9 26 P2.2 ; A14D10 27 P2.3 ; A15D11 28 P2.4 ; A16D12 29 P2.5 ; A17D13 30 P2.6 ; A18D14 31 P2.7 ; A19D15 32 PSEN/ 33 ALE ; PROG/ 34 CAN TxD 35 EA/ ; Vpp ; WAIT 36 P0.7 ; A11D7 37 P0.6 ; A10D6 38 P0.5 ; A9D5 39 P0.4 ; A8D4 40 P0.3 ; A7D3 41 P0.2 ; A6D2 42 P0.1 ; A5D1 43 P0.0 ; A4D0 Preliminary specification XA-C3 Function (see Note) ...
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... All active–low signals are indicated by a “/” symbol 2000 Jan 25 Figure 2. 44-pin PLCC package Pin 23 P2.5 ; A17D13 4 P2.6 ; A18D14 25 P2.7 ; A19D15 26 PSEN/ 27 ALE ; PROG/ 28 CAN TxD 29 EA/ ; Vpp ; WAIT 30 P0.7 ; A11D7 31 P0.6 ; A10D6 32 P0.5 ; A9D5 33 P0.4 ; A8D4 34 P0.3 ; A7D3 35 P0.2 ; A6D2 36 P0.1 ; A5D1 37 P0.0 ; A4D0 38 VDD 39 VSS 40 P1.0 ; WRH P1.4 ; SPIRx 4 Preliminary specification XA-C3 Function (see Note) ...
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... WRL/ RD/ 2000 Jan XTAL1 XTAL2 RST WAIT; EA/ PP PSEN/ ALE; PROG/ CAN Tx CAN Rx Figure 3. Logic Symbol 5 Preliminary specification XA-C3 ADDRESS AND 16-BIT DATA BUS INCLUDING 32 DMA CHANNELS FOR 32 CAL MESSAGE OBJECTS T2EX; INT2/ T2/SPICLK SPITx SPIR WRH/ SU01316 ...
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... OTP DATA BUS 1024 BYTES DATA RAM 512 BYTES XRAM CTL MESSAGE OBJECTS MMR BUS 32 CTL DMA CHANNELS 32 OBJECT PTRS 32 ID FILTERS 2.0B CAN/DLL PELICAN CORE PORTS 0–3 Figure 4. XA-C3 Simplified Block Diagram 6 Preliminary specification XA-C3 UART0 SPI TIMER 0 TIMER 1 TIMER 2 WATCHDOG TIMER SU01317 ...
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... The operation of Port 3 pins as inputs or outputs depends upon the Port configuration selected. 9. Each Port pin is configured independently. Refer to the sections on I/O Port configuration and DC Electrical Characteristics for details. I RxD0: Receiver serial input of UART 0. O TxD0: Transmitter serial output of UART 0. I INT0/: External interrupt 0 input. I INT1/: External interrupt 1 input. 7 Preliminary specification XA-C3 ...
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... CAN Receive Data input: CAN serial receiver input to the SJA1000 PeliCAN core. O CAN Transmit Data output: CAN serial transmitter output from the SJA1000 PeliCAN core. I Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock generator circuits. O Crystal 2: Output from the oscillator amplifier. 8 Preliminary specification XA-C3 ...
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... RS1 RS0 307 306 305 304 303 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 9 Preliminary specification XA-C3 RESET VALUE 07h (Note 1) – – – FFh (Note 2) DR0 DRA1 DRA0 EFh (Note 2) CR0 CRA1 CRA0 – – – F0h – ...
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... PRE2 PRE1 PRE0 – – 10 Preliminary specification XA-C3 RESET VALUE 30A 309 308 00h BR0 OE0 STINT0 xxh 00h 00h 00h PT0 CM PZ 21A 219 218 ...
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... R/W* 276h R/W 278h RO 27Ah RO 27Eh R/W MEMORY INTERFACE (MIF) REGISTERS 293h R/W 292h R/W 291h R/W 290h R/W 11 Preliminary specification XA-C3 ACCESS Reset Value Word only xxxxh Word only x x00b Word only xxxxh Word only x x000b Byte 00000xxxb Word only xxxxh Byte 00000xxxb Byte 00xxxxxxb Word 0000h ...
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... XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor XA-C3 TIMER/COUNTERS The XA has two standard 16–bit enhanced Timer/Counters: Timer 0 and Timer 1. Additionally, it has a third 16–bit Up/Down timer/counter, T2. A central timing generator in the XA core provides the time– ...
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... When Timer Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator fact, in any application not requiring an interrupt. TR1 TF0 TR0 IE1 IT1 13 Preliminary specification XA-C3 LSB IE0 IT0 SU00604C ...
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... T2CAPH to be reloaded into timer registers TL2 and TH2, respectively. A logic ‘0’ at pin T2EX causes Timer 2 to count down. When counting down, the timer value is compared to the 16–bit value contained in T2CAPH and T2CAPL. When the value is equal, the 14 Preliminary specification XA-C3 LSB T2/ RL2/ SU001326 ...
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... T2EX pin X 16–bit capture X Baud rate generator — — — — Figure 9. Timer 0 and 1 Extended Status (TSTAT) — RCLK1 TCLK1 — Figure 10. Timer 2 Mode Control (T2MOD) 15 Preliminary specification XA-C3 MODE LSB T1OE — T0OE SU00612B LSB — T2OE DCEN SU00610B ...
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... Figure 12. Timer 2 in Auto-Reload Mode (DCEN = 0) 2000 Jan 25 TL2 TH2 (8-bits) (8-bits) Control TR2 Capture T2CAPL T2CAPH Figure 11. Timer 2 in Capture Mode TL2 TH2 (8-bits) (8-bits) Control TR2 Reload T2CAPL T2CAPH Control 16 Preliminary specification XA-C3 TF2 Timer 2 Interrupt EXF2 SU01327 TF2 Timer 2 Interrupt EXF2 SU01328 ...
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... PIN CONTROL TR2 Figure 13. Timer 2 Auto Reload Mode (DCEN = 1) 2000 Jan 25 (DOWN COUNTING RELOAD VALUE) FFH FFH OVERFLOW TL2 TH2 T2CAPL T2CAPH (UP COUNTING RELOAD VALUE) 17 Preliminary specification XA-C3 TOGGLE EXF2 TF2 INTERRUPT COUNT DIRECTION DOWN T2EX PIN SU01329 ...
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... When coming out of a hardware Reset, the software should load the autoload register and then feed the watchdog (i.e., cause an autoload). If the watchdog is running and happens to underflow at the time the External Reset is applied, the watchdog time–out flag will be cleared. 18 Preliminary specification XA-C3 4096 t and OSC DIVISOR 0 32 ...
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... PRE0 — — WDRUN Figure 14. Watchdog Timer in XA-C3 The UART baud rate is determined by either a fixed division of the oscillator (in UART–0 Modes 0 and the Timer 1 or Timer 2 overflow rate (in UART–0 Modes 1 and 3). Timer 1 defaults to clock UART–0. Timer 2 can clock UART–0 through T2CON via bits RCLK0 (T2CON[5]) and/or TCLK0 (T2CON[4]) ...
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... NOTES: 1. The maximum baud rate for UART–0 in Mode osc /64. 2. The lowest possible baud rate (for a given oscillator frequency and N value) may be found by using a timer reload value Preliminary specification XA-C3 osc /16. In Mode 2, f TCLK ...
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... The 9–bit mode requires that the 9th information bit indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 16. 21 Preliminary specification XA-C3 T2CON[5] T2CON[4] RCLK0 TCLK0 SCR[3] ...
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... UART variable 0 2 9-bit UART f /32 OSC 1 3 9-bit UART variable Figure 16. Serial Port Control (S0CON) Register 22 Preliminary specification XA-C3 S0ADDR = 1100 0000 S0ADEN = 1111 1001 Given = 1100 0XX0 S0ADDR = 1110 0000 S0ADEN = 1111 1010 Given = 1110 0X0X S0ADDR = 1110 0000 ...
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... External PROGRAM/DATA bus provides 16 bit width in a 20–bit ADDRESS space. RESET Refer to Figure 19 for a recommended Reset circuit example. SOME TYPICAL VALUES FOR R AND 100K 1 1.0M 0.1 F (ASSUMING THAT THE V Figure 19. Recommended Reset Circuit 23 Preliminary specification XA- ONLY IN STOP MODE 2, 3 BIT if 0, sets FE S0STAT OE0 STINT0 ...
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... Software Interrupts – demote the priority level of a running Event Interrupt below the lowest Event priority level (i.e., 9), thereby permitting lower priority Event Interrupts to run. Trap Interrupts –accomplish multi–tasking services, such as RTOS, via non–maskable interrupts. 24 Preliminary specification XA-C3 ; EA/} pin becomes a pp SU01333 ...
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... Exception Interrupts are standardized within the XA core. For core details refer to the XA User Guide. Interrupt Structures Four tables provide details of the XA-C3 Interrupt structure. Table 14 defines the sixteen interrupt priority levels Table 15 describes the Exception and Trap Interrupts Table 16 explains the Event Interrupts ...
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... SWE7 ; SWE[6] 0114–0117 SWE6 ; SWE[5] 0110–0113 SWE5 ; SWE[4] 010C–010F SWE4 ; SWE[3] 0108–010B SWE3 ; SWE[2] 0104–0107 SWE2 ; SWE[1] 0100–0103 SWE1 ; SWE[0] 26 Preliminary specification XA-C3 INTERRUPT ARBITRATION PRIORITY RANKING PX0 ; IPA0[2:0] 2 PT0 ; IPA0[6:4] 3 PX1 ; IPA1[2:0] 4 PT1 ; IPA1[6:4] 5 PT2 ; IPA2[2:0] 6 PBUFF ...
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... 5.5V –0 5.0V 2 0.45V 3.2mA 5. –100mA Preliminary specification XA-C3 LIMITS UNIT TYP MAX 100 A 150 A V 0.22V 0 –25 – –650 A 0.22V V DD ...
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... This variable represents the programmed length of an entire code read cycle with ALE. This time is determined by the CRA1 and CRA0 bits in the BTRL register the total bus cycle duration (2 if CRA1 CRA1 CRA1/0 = 10, and 5 if CRA1/0 = 11). 28 Preliminary specification XA-C3 UNIT MAX 32 MHz ns ns ...
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... This parameter is provided for peripherals that have the data clocked in on the falling edge of the WR/ strobe. This is not usually the case, and in most applications this parameter is not used. 6. Please note that the XA–C3 requires that extended data bus hold time (WM0 = used with External bus write cycles. 29 Preliminary specification XA-C3 ...
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... PSEN MULTIPLEXED A4–A19 ADDRESS AND DATA UNMULTIPLEXED ADDRESS * D0–D15 Figure 22. External PROGRAM Memory Read Cycle (Non-ALE Cycle) 2000 Jan 25 t LLPL t PLPH t PLIV t LLAX t PXIZ t PLAZ t PXIX * INSTR IN t IXUA t AVIVA A1–A3 * INSTR IN A1–A3 30 Preliminary specification XA-C3 SU00946 t AVIVB A1–A3 SU01345 ...
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... ADDRESS A4–A19 AND DATA t AVWL UNMULTIPLEXED ADDRESS * D0–D15 2000 Jan LLRL RLRH t RHDZ t RLDV t RHDX * DATA IN t AVDVA A1– WLWH LLWL t QVWX * DATA OUT t A1–A3 Figure 24. External DATA Memory Write Cycle 31 Preliminary specification XA-C3 t DXUA SU01346 t WHQX UAWH SU01347 ...
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... Figure 26. External Clock Drive 0.2V +0.9 DD 0.2V –0.1 DD –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. DD Figure 27. AC Testing Input/Output +0.1V TIMING REFERENCE POINTS –0.1V /V level occurs Figure 28. Float Waveform 32 Preliminary specification XA-C3 SU00709A SU00842 SU00703A V –0. +0. 20mA SU00011 ...
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... Note: All other pins are disconnected Figure 31. I vs. Frequency 5. –0.5 0.7V DD 0.2V –0 CHCX CHCL CLCX CLCH t CL Tests in Active and Idle Modes DD 33 Preliminary specification XA- RST EA XTAL2 XTAL1 V SS SU00590B Test Condition, Idle Mode DD SU01334 SU00608A ...
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... All further programming of the EPROM is disabled. When, in addition to the above, security bits 1 and 2 are programmed, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all External PROGRAM memory execution is disabled. (See Table 21). 34 Preliminary specification XA-C3 ...
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... OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor XA-C3 OVERVIEW Introduction The XA- member of the Philips XA (eXtended Architecture) family of high performance 16–bit single–chip microcontrollers. Combined in the XA-C3 are an array of standard microcontroller peripherals, a powerful CAN 2.0A/B controller, and a unique CAN ” ...
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... DLC IFS Inter F rame S pace CTL/CAN Functionality of the XA-C3 Message Objects / Message Management The XA-C3 allows the User to define separate CTL/CAN Message Objects. Any of these 32 objects can be designated as either a Receive or Transmit objects. Any/all of the (up to 32) Receive Objects may be enabled to hardware assemble multi frame “Fragmented” messages. For Receive Objects so enabled, CTL/CAN hardware interrupts the XA-C3 only at the completion of a multi– ...
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... ID. An alternate option bases transmit pre–arbitration exclusively on transmit object number, i.e., independent of arbitration ID. Remote Frame Handling The XA-C3 supports Remote CAN Frames. MEMORY MAPS Data Memory Space 1K byte of internal data memory (Scratch Pad) populates the very bottom of data memory space, in Segment 0 by definition. The Memory Mapped Registers and the on– ...
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... TSEG1.2 TSEG1.1 TSEG1.0 SJW.1 SJW.0 Bus Off Hardware reset Test mode (Refer to XA-C3 User Guide, Sections 2.2.2.1 and 2.7.1.2) CANCMR: CAN Command Register Address: MMR base + 270h Access: Read/Write, no R/M/W, Byte or Word Access. Hardware can set bit 0. Reset value: 01h 4 3 Reserved SLPEN ...
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... Receive Message Objects and the Receive Process During reception, the XA-C3 will store the incoming message in a temporary (13–byte) buffer. Once it is determined that a complete, error–free CAN frame has been successfully received, the XA-C3 will initiate the acceptance filtering (“Mask and Match”) process. If acceptance filtering produces a Match with an enabled receive object’ ...
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... Reset value: xxxxh Msk23 Msk22 Msk21 Msk20 Msk19 Msk18 Access: Read, write. Word access only. Reset value: xxxxxxxxxxxxx000b (unused bits are always read as ‘0’) 40 Preliminary specification XA-C3 Mid1 Mid0 MIDE Msk1 Msk0 x x IDE Mid1 Mid0 MIDE Msk1 Msk0 IDE 5 4 ...
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... Message Object. This is specified in the object’s MnBLR register. The User is also required to set up the size of each buffer in the MnBSZ register. The XA-C3 provides a total of 512 bytes of on–chip message buffer RAM (XRAM) which may contain part or all of the CAN/CTL (transmit & receive) message buffer space. See Section entitled On-Chip Message Buffer RAM (XRAM) on page 55 for details ...
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... Match and Mask will not change as a result of an accepted incoming frame (see Figure 38). Frame Info Data byte 1 Data byte 2 Data byte 3 Data byte 4 Data byte 5 Data byte 6 Data byte 7 Data byte 8 Figure 38. Memory Image for Non–Fragmented Messages 42 Preliminary specification XA- Direction of increasing address dd ...
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... The top location of the buffer is determined by the size of the buffer as specified in MnBSZ. The XA-C3 automatically receives, checks and reassembles Fragmented messages automatically. When the FRAG bit is set on a particular message, the message handler hardware will use the Fragmentation information contained in Data Byte 1 of each frame ...
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... Byte”, as defined by the protocol specification, in byte offset 0 of the Tx object’s message buffer. Bit position [ don’t care, because the XA-C3 will automatically insert the toggle bit value from the incoming frame into the toggle bit position of the outgoing auto– ...
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... CAN arbitration ID field will be selected for transmission. If more than one pending transmit message share the same CAN identifier, then secondary priority will be based on XA-C3 Message Object numbers, with the lowest numbered object winning access. The winning message will then be output onto the CAN bus where it will compete for access with other transmitting nodes. Pre– ...
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... Figure 42. Format for Storing the Tx Frame Info in MnMSKH Transmission of Fragmented Messages The XA-C3 does not handle the transmission of Fragmented messages in hardware the User’s responsibility to write each frame of a Fragmented message to the transmit buffer, enable the object for transmission, and wait for a completion before writing the next frame to the message buffer ...
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... There is an additional mechanism that prevents corruption of a message that is being transmitted transmission is ongoing for a Message Object, the XA-C3 hardware will prevent the User from clearing the OBJ_EN bit in the object’s MnCTL register. Bit 5 Bit 4 ...
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... At that time, st the ‘0’ location of the 1 buffer will indicate how many bytes are stored there, and likewise for the second buffer (or third or so on). Note that option 2 is far more efficient and can be implemented with very few instructions. 48 Preliminary specification XA-C3 ...
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... If for some reason the DMA is unable to gain access to the bus for a long period of time, the pre–buffer could overflow. In this event, the XA-C3 will stop accepting the new message. That is, once the five pre–buffer bytes are full, subsequent incoming bits will be ignored. ...
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... CANINTFLG (CAN Interrupt Flag Register) Address: MMR base + 228h Access: Read/Clear, byte or word Reset Value: 00h CANINTFLG – – – FERIF MERIF RBFIF FERIF Frame Error Interrupt Flag (this bit is Read–Only, and must be cleared in FESTR) 50 Preliminary specification XA- TMCIF RMCIF ...
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... Object Number 1 0 ERRWE ERRPE MCPLH (Message Complete Status Flags High) Address: MMR base + 226h Access: Read/Clear, byte or word Reset Value: 0000h 51 Preliminary specification XA-C3 Error Warning Enable (0 = disabled enabled) Error Passive Enable (0 = disabled enabled Object Number objects whose INT_EN bits are set currently have a message complete condition ...
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... Reset Value: 00h 4 3 State ALCR (Arbitration Lost Capture Register) Address: MMR base + 27Ah Access: Read, write, R/M/W, byte or word Reset Value: 00h 4 3 This register should be read before enabling the Arbitration Lost interrupt. 52 Preliminary specification XA- Obj20 Obj19 Obj18 Obj17 Obj16 5 4 ...
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... CAN/CTL blocks (including the CMI) at the top level. XA-C3 Power–Down Mode If a transition of the CAN RxD input occurs when the XA- Power–Down mode, the CPU will enter Idle mode (after a 9892 clock delay), and the CCB and Message Handler circuits will be activated to receive and process the incoming frame ...
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... All of the logic required to implement everything discussed in this section will be in the CCB. MEMORY INTERFACE UNIT General Description The XA-C3 memory interface (MIF) unit provides interfaces to generic memory devices such as SRAM, flash, and EPROM. The timing of memory cycles, including different strobe widths, is programmable by software. ...
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... MBXSR register, the XRAM and all 32 message buffers must reside in the same 64K byte data memory segment. Since the XA-C3 only provides address lines A1 – A19 for accessing External memory, all External memory addresses must be within the lowest 1M byte of address space. Therefore, if there is ...
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... XRAMB[7:1] 0 xy0000h Segment xy in Data Memory Space a23 a16 MBXSR[7:0] XRAM a23 a16 MBXSR[7:0] xy0000h Access: Read, write. Reset value: FFh 4 3 Access: Read, write Reset value: FEh 56 Preliminary specification XA-C3 a0 MnBLR 00h SU01342 a15 a0 MnBLR a15 XRAMB[7:1] 0 00h SU01343 2 1 ...
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... Rsvd SPC3 SPICLK = (CClk (SPICFG[3: SPIDATA (MMR) Address: MMR base + 262h Access: Read, write, byte or word Reset value: 00h 4 3 Data Access: Read, write, byte or word Reset value: 00h 57 Preliminary specification XA- XRE – – – CR0 CRA1 ...
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... Cycle finished, cleared by hardware and on reset 1 = Start SPB2 – SPB0 Number of SPI bits transceived = SPICFG[6: 2000 Jan SPB0 SPFG Rsvd Rsvd Reserved bits, write only zeros SPIDL SPI TxD idle state 0 = idle low 1 = idle high 58 Preliminary specification XA- Rsvd SPIDL ...
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... Philips Semiconductors XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor LQFP44: plastic low profile quad flat package; 44 leads; body 1.4 mm 2000 Jan 25 59 Preliminary specification XA-C3 SOT389-1 ...
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... Philips Semiconductors XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor PLCC44: plastic leaded chip carrier; 44 leads 2000 Jan 25 60 Preliminary specification XA-C3 SOT187-2 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors 2000 Jan 25 [1] Copyright Philips Electronics North America Corporation 2000 Document order number: 61 Preliminary specification XA-C3 All rights reserved. Printed in U.S.A. Date of release: 01-00 9397 750 06805 ...