XA-G30 NXP Semiconductors, XA-G30 Datasheet - Page 12
Manufacturer Part Number
The Philips Semiconductors XA (eXtended Architecture) family of 16-bit single-chip microcontrollers is powerful enough to easily handle the requirements of high performance embedded applications, yet inexpensive enough to compete in the market for hi
New Timer-Overflow Toggle Output
In the XA, the timer module now has two outputs, which toggle on
overflow from the individual timers. The same device pins that are
used for the T0 and T1 count inputs are also used for the new
overflow outputs. An SFR bit (TnOE in the TSTAT register) is
associated with each counter and indicates whether Port-SFR data
or the overflow signal is output to the pin. These outputs could be
used in applications for generating variable duty cycle PWM outputs
(changing the auto-reload register values). Also variable frequency
(Osc/8 to Osc/8,388,608) outputs could be achieved by adjusting
the prescaler along with the auto-reload register values. With a
30.0MHz oscillator, this range would be 3.58Hz to 3.75MHz.
Timer 2 in the XA is a 16-bit Timer/Counter which can operate as
either a timer or as an event counter. This is selected by C/T2 in the
special function register T2CON. Upon timer T2 overflow/underflow,
the TF2 flag is set, which may be used to generate an interrupt. It
can be operated in one of three operating modes: auto-reload (up or
down counting), capture, or as the baud rate generator (for either or
both UARTs via SFRs T2MOD and T2CON). These modes are
shown in Table 1.
In the capture mode there are two options which are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, then timer 2 is a 16-bit timer or
counter, which upon overflowing sets bit TF2, the timer 2 overflow
bit. This will cause an interrupt when the timer 2 interrupt is enabled.
If EXEN2 = 1, then Timer 2 still does the above, but with the added
feature that a 1-to-0 transition at external input T2EX causes the
current value in the Timer 2 registers, TL2 and TH2, to be captured
into registers RCAP2L and RCAP2H, respectively. In addition, the
transition at T2EX causes bit EXF2 in T2CON to be set. This will
cause an interrupt in the same fashion as TF2 when the Timer 2
interrupt is enabled. The capture mode is illustrated in Figure 7.
2002 Mar 25
XA 16-bit microcontroller family
512 B RAM, watchdog, 2 UARTs
Reset Value: 00H
T2CON.1 C2 or T2
T2CON.0 CP or RL2 Capture/Reload flag.
If CP/RL2=0, EXEN2=1 auto reloads occur with either Timer 2 overflows or negative transitions at T2EX.
Timer 2 overflow flag. Set by hardware on Timer/Counter overflow. Must be cleared by software.
TF2 will not be set when RCLK0, RCLK1, TCLK0, TCLK1 or T2OE=1.
Timer 2 external flag is set when a capture or reload occurs due to a negative transition on T2EX (and
EXEN2 is set). This flag will cause a Timer 2 interrupt when this interrupt is enabled. EXF2 is cleared by
Receive Clock Flag.
Transmit Clock Flag. RCLK0 and TCLK0 are used to select Timer 2 overflow rate as a clock source for
UART0 instead of Timer T1.
Timer 2 external enable bit allows a capture or reload to occur due to a negative transition on T2EX.
Start=1/Stop=0 control for Timer 2.
Timer or counter select.
1=External event counter (falling edge triggered)
If CP/RL2 & EXEN2=1 captures will occur on negative transitions of T2EX.
If RCLK or TCLK=1 the timer is set to auto reload on Timer 2 overflow, this bit has no effect.
Figure 4. Timer/Counter 2 Control (T2CON) Register
T2CON is set, the timer registers will also be reloaded and the EXF2
Auto-Reload Mode (Up or Down Counter)
In the auto-reload mode, the timer registers are loaded with the
16-bit value in T2CAPH and T2CAPL when the count overflows.
T2CAPH and T2CAPL are initialized by software. If the EXEN2 bit in
flag set when a 1-to-0 transition occurs at input T2EX. The
auto-reload mode is shown in Figure 8.
In this mode, Timer 2 can be configured to count up or down. This is
done by setting or clearing the bit DCEN (Down Counter Enable) in
the T2MOD special function register (see Table 1). The T2EX pin
then controls the count direction. When T2EX is high, the count is in
the up direction, when T2EX is low, the count is in the down
Figure 8 shows Timer 2, which will count up automatically, since
DCEN = 0. In this mode there are two options selected by bit
EXEN2 in the T2CON register. If EXEN2 = 0, then Timer 2 counts
up to FFFFH and sets the TF2 (Overflow Flag) bit upon overflow.
This causes the Timer 2 registers to be reloaded with the 16-bit
value in T2CAPL and T2CAPH, whose values are preset by
software. If EXEN2 = 1, a 16-bit reload can be triggered either by an
overflow or by a 1-to-0 transition at input T2EX. This transition also
sets the EXF2 bit. If enabled, either TF2 or EXF2 bit can generate
the Timer 2 interrupt.
In Figure 9, the DCEN = 1; this enables the Timer 2 to count up or
down. In this mode, the logic level of T2EX pin controls the direction
of count. When a logic ‘1’ is applied at pin T2EX, the Timer 2 will
count up. The Timer 2 will overflow at FFFFH and set the TF2 flag,
which can then generate an interrupt if enabled. This timer overflow,
also causes the 16-bit value in T2CAPL and T2CAPH to be
reloaded into the timer registers TL2 and TH2, respectively.
A logic ‘0’ at pin T2EX causes Timer 2 to count down. When
counting down, the timer value is compared to the 16-bit value
contained in T2CAPH and T2CAPL. When the value is equal, the