XA-H3 NXP Semiconductors, XA-H3 Datasheet - Page 19

• Manufacturer Part Number: XA-H3
• Description: The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Each memory bank and associated chip select is capable of
supporting a 1 MB address space (six chip selects can thus support
6 MB of SRAM and other generic devices.)
Bus Interface Pins
For the following discussion, see Figure 3.
Chip Select Pins
There are six chip select pins (CS5 – CS0)mapped to six sets of
bank control registers. The following attributes are individually
programmable for each bank and associated chip select : bank
Clock Output
The CLKOUT pin allows easier external bus interfacing in some
situations. This output reflects the XTALIn clock input to the XA
(referred to internally as CClk or System Clock), but is delayed to
match the external bus outputs and strobes. The default is for
1999 Sep 24
WARNING: On the external bus, ALL XA-H3 reads are 16-bit Reads. If the CPU instruction only specifies 8-bits, then the CPU uses the appropriate
byte, and discards the extra byte. Thus “8-Bit Reads” and “16-Bit Reads” appear to be identical on the bus. On an 8-bit bus, this will appear
as two consecutive 8-bit reads even though the CPU instruction specified a byte read.
Some 8-bit I/O devices (especially FIFOs) cannot operate correctly with 2 bytes being Read for a 1 Byte Read. The most common (and least
expensive) solution is to operate these 8-bit devices on a 16-bit bus, and access them in software on all odd byte (or all even byte) boundaries.
An added benefit of this technique is that byte reads are faster than on an 8-bit bus, because only 1 word is fetched (a single read) instead of
2 consecutive bytes.
CMOS 16-bit highly integrated microcontroller
XA-H3
Figure 3. Memory Bus Interface Signal Pins
SRAM Controller
Dynamic Bus Sizing
Dynamic Bus Timing
Memory Controller
19
The Memory Interface can be programmed to support both Intel
style and 68000 bus style SRAMs and peripherals.
on/off, address range, external device access time, detailed bus
strobe sequence, and bus width.
CLKOUT to be output enabled at reset, but it may be turned off
(tri-state disabled) by software via the MICFG MMR.
WARNING: The capacitive loading on this output must not
exceed 40 pf.
A19–A0
D15–D0
CS5 (or P3.1, RTS1)
CS4 (or P3.0, RTClk1)
CS3
CS2
CS1
CS0
ClkOut
BHE
BLE
OE
WE
WAIT, SIZE16
Preliminary specification
SU01238
XA-H3