XA-H3 NXP Semiconductors, XA-H3 Datasheet - Page 23

• Manufacturer Part Number: XA-H3
• Description: The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Four UARTS
I/O Port Output Configuration
Port input/output configurations are the same as standard XA ports:
open drain, quasi-bidirectional, push-pull, and off (off means tri-state
1999 Sep 24
Segment Register: Holds A23–A16 (the current segment) of the
24-bit data buffer address.
Buffer Base Register: Holds a pointer (A15–A8) to the lowest byte
in the memory buffer.
Buffer Bound Register: Points to the first out-of-bounds address
above a circular buffer.
Address Pointer Register: Points to a single byte or word in the
data buffer in memory. The 24-bit DMA address is formed by
concatenating the contents of the Segment Register [A23–A16]
with the contents of the Address Pointer Register [A15–A0].
Byte Count Register: Holds the initial number of bytes to be
transferred. In Tx Chaining mode, this register is not used
because the byte count is brought into the byte counter from
buffer headers in memory.
FIFO Control & Status Register: Holds the queuing order and
full/empty status for the Data FIFO Registers.
Data FIFO Registers: A four-byte data FIFO buffer internal to the
DMA channel.
Rx Char Time Out Register (RxCTOR, Rx DMA channels only):
Holds the initial value for an 8-bit character timeout countdown
timer which can generate an interrupt.
Asynchronous transfers up to
5, 6, 7, or 8 data bits per character
1, 1.5, or 2 Stop bits per character
Even or Odd parity generate and check
Parity, Rx Overrun, and Framing Error detection
Break detection
Programmable Baud Rate Generator
Auto Echo and Loopback Modes
CMOS 16-bit highly integrated microcontroller
230.4 kbps
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Hi-Z, and allows the pin to be used as an input. WARNING: At
power on time, from the time that power coming up is valid, the
P3.2_Timer0_ResetOut pin may be driven low for any period from
zero nanoseconds up to 258 system clocks. This is true
independently of whether ResetIn is active or not.
Power Reduction Modes
The XA-H3 supports Idle and Power Down modes of power
reduction. The idle mode leaves most peripherals running in order to
allow them to activate the processor when an interrupt is generated.
The power down mode stops the oscillator in order to absolutely
minimize power. The processor can be made to exit power down
mode via a reset or one of the external interrupt inputs (INT0 or
INT1). This will occur if the interrupt is enabled and its priority is
higher than that defined by IM3 through IM0. In power down mode,
the power supply voltage may be reduced to the RAM keep-alive
voltage VRAM. This retains the RAM, register, and SFR contents at
the point where power down mode was entered. WARNING: V
must be raised to within the operating range before power down
mode is exited.
Interrupts
In the XA architecture, all exceptions, including Reset, are handled in
the same general exception structure. The highest priority exception is
of course Reset, and it is non-maskable. All exceptions are vectored
through the Exception Vector Table in low memory. Coming out of
Reset, these vectors must be stored in non-volatile memory based at
location 000000. Later in the boot sequence, SRAM or other memory
can be mapped into this address space if desired. There is a feature
in the XA-H3 Memory Controller called “Bank Swap” that supports
replacing the ROM vector table and other low memory with RAM. See
the XA-H3 User Manual for details.
The XA-H3 has a standard XA CPU Interrupt Controller,
implemented with 15 Maskable Event Interrupts. Event Interrupts
are defined as maskable interrupts usually generated by hardware
events. However, in the XA-H3, 4 of the 15 Event Interrupts are
generated by software writing directly to the interrupt flag bit. These
4 interrupts are referred to as High Priority Software Interrupts.
See the IC25 XA Data Handbook for a full explanation of the
exception structure, including event interrupts, of the XA CPU.
Because the High Priority Software Interrupts are specific to the
XA-H3, they are explained in the XA-H3 User Manual .
Preliminary specification
XA-H3
DD