XA-H4 NXP Semiconductors, XA-H4 Datasheet - Page 22

• Manufacturer Part Number: XA-H4
• Description: The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 4. Memory interface control registers
EIGHT CHANNEL DMA CONTROLLER
The XA-H3/H4 has eight DMA channels; one Rx DMA channel
dedicated to each USART Receive (Rx) channel, and one Tx DMA
channel dedicated to each USART Transmit (Tx) channel. All DMA
channels are optimized to support memory efficient circular data
buffers in external memory. All DMA channels can also support
traditional linear data buffers.
Table 5. Tx DMA modes summary
1999 Sep 24
MRBH
MRBL
MICFG MIF Configuration
MBCL
BiCFG
BiAM
BiTMG
RFSH
Non-SDLC/HDLC
Tx Chaining
SDLC/HDLC
Tx Chaining
Stop on TC
Periodic Interrupt
Single-chip 16-bit microcontroller
Mode
“MMR Base Address” High
“MMR Base Address” Low
Memory Bank Configuration
Lock
Bank i Configuration
Bank i Base Address/DRAM
Address Multiplexer Control
Bank i Timing
Refresh Timing
Register Name
Header in memory
Header in memory
Processor loads Byte Count Register (for
each fragment)
Porcessor loads Byte Count Register
(only once)
Byte Count Source
SFR
8 bits
SFR
8 bits
MMR
8 bits
MMR
8 bits
MMR
8 bits
MMR
8 bits
MMR
8 bits
MMR
8 bits
Type
Reg
This SFR is used to relocate the MMRs. It contains address bits a23 – a16 of the base
address for the 4 kB Memory Mapped Register space. See the XA-H4 User Manual for
using this SFR to relocate the MMRs.
Contains address bits a15 – a12 of the base address for the 4 kB Memory Mapped
Register space.
Contains the ClkOut Enable bit.
Contains the bits for locking and unlocking the BiCFG Registers.
Contains the size, type, bus width, and enable bits for Memory Bank i.
Contains the base address bits and DRAM address multiplex control bits for
Memory Bank i.
Contains the timing control bits for Memory Bank i.
Contains the refresh time constant and DRAM Refresh Timer enable bit.
On stop
End of packet (not end
of fragment)
Byte count completed
(Tx DMA stops)
When Byte Counter
reaches zero and is
reloaded by DMA
hardware from the byte
count register.
Maskable Interrupt
22
Transmit DMA Channel Modes
The four Tx channels have four DMA modes specifically designed
for various applications of the attached USARTs. These modes are
summarized in Table 5. Full details for all DMA functions can be
found in the DMA chapter of the XA-H4 User Manual .
DMA channel picks up header from memory at the
end of transmission. If the byte count in the header
is greater than zero, then DMA transmits the number
of bytes specified in the byte count. If byte count
equals 0, then a maskable interrupt is generated.
This process repeats until the byte count in the data
header is zero. See XA-H4 User Manual for details.
Same as above, except DMA header distinguishes
between fragment of packet and full pack. See
XA-H4 User Manual for details.
Processor loads byte count into DMA. DMA sends
that number of bytes, generates maskable interrupt,
and stops.
DMA runs until commanded to stop by processor.
Every time byte counter rolls over, a new
maskable interrupt is generated.
Description
Description
Preliminary specification
XA-H4