EP4CE15F17C9L Altera Corporation, EP4CE15F17C9L Datasheet - Page 20

• Manufacturer Part Number: EP4CE15F17C9L
• Description: IC CYCLONE IV FPGA 15K 256FBGA
• Manufacturer: Altera Corporation
• Series: CYCLONE® IV Er

Specifications of EP4CE15F17C9L

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 165
• Number Of Gates: -
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status: Contains lead
• Rohs Status: RoHS non-compliant

1–20
Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 4 of 4)—Preliminary
Cyclone IV Device Handbook,
Volume 3
PLD-Transceiver Interface
Interface speed
(F324 and smaller
package)
Interface speed
(F484 and larger
package)
Digital reset pulse
width
Notes to
(1) This specification is valid for transmitter output jitter specification with a maximum total jitter value of 112 ps, typically for 3.125 Gbps SRIO and XAUI
(2) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter Only mode. The minimum reconfig_clk frequency
(3) The device cannot tolerate prolonged operation at this absolute maximum.
(4) The rate matcher supports only up to ±300 parts per million (ppm).
(5) Supported for the N148, F169, and F324 device packages only.
(6) Supported for the F484, F672, and F896 device packages only. Pending device characterization.
(7) To support CDR ppm tolerance greater than ±300 ppm, implement ppm detector in user logic and configure CDR to Manual Lock Mode.
(8) Asynchronous spread-spectrum clocking is not supported.
(9) For the EP4CGX30 (F484 package only), EP4CGX50, and EP4CGX75 devices, the CDR ppl tolerance is ±200 ppm.
(10) Time taken until pll_locked goes high after pll_powerdown deasserts.
(11) Time that the CDR must be kept in lock-to-reference mode after rx_analogreset deasserts and before rx_locktodata is asserted in manual mode.
(12) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode
(13) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode.
(14) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode.
protocols.
is 37.5 MHz if the transceiver channel is configured in Receiver Only or Receiver and Transmitter mode.
automatic mode
Description
Symbol/
Table
1–21:
(Figure
1–3).
Conditions
—
—
—
Min
25
25
Typ
—
—
C6
156.25
Max
125
Minimum is 2 parallel clock cycles
Min
25
25
C7, I7
(Figure
Typ
—
—
Chapter 1: Cyclone IV Device Datasheet
1–2), or after rx_freqlocked signal goes high in
156.25
Max
125
November 2011 Altera Corporation
Min
25
25
Switching Characteristics
Typ
—
—
C8
156.25
Max
125
MHz
MHz
Unit