EP4CE15F17C9L Altera Corporation, EP4CE15F17C9L Datasheet - Page 25

• Manufacturer Part Number: EP4CE15F17C9L
• Description: IC CYCLONE IV FPGA 15K 256FBGA
• Manufacturer: Altera Corporation
• Series: CYCLONE® IV Er

Specifications of EP4CE15F17C9L

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 165
• Number Of Gates: -
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status: Contains lead
• Rohs Status: RoHS non-compliant

Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Table 1–25. PLL Specifications for Cyclone IV Devices
November 2011 Altera Corporation
t
t
t
t
t
t
t
t
f
t
Notes to
(1) This table is applicable for general purpose PLLs and multipurpose PLLs.
(2) You must connect V
(3) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
(4) The V
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
(6) Peak-to-peak jitter with a probability level of 10
(7) With 100-MHz scanclk frequency.
(8) The cascaded PLLs specification is applicable only with the following conditions:
(9) PLL cascading is not supported for transceiver applications.
(8),
DLOCK
OUTJITTER_PERIOD_DEDCLK
OUTJITTER_CCJ_DEDCLK
OUTJITTER_PERIOD_IO
OUTJITTER_CCJ_IO
PLL_PSERR
ARESET
CONFIGPLL
SCANCLK
CASC_OUTJITTER_PERIOD_DEDCLK
■
■
(9)
standard.
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f
than 200 ps.
to the intrinsic jitter of the PLL when an input jitter of 30 ps is applied.
Upstream PLL—0.59 MHz  Upstream PLL bandwidth < 1 MHz
Downstream PLL—Downstream PLL bandwidth > 2 MHz
Table
CO
Symbol
frequency reported by the Quartus II software in the PLL Summary section of the compilation report takes into consideration the V
1–25:
(6)
(6)
(6)
CCD_PLL
(6)
to V
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
areset is deasserted)
Dedicated clock output period jitter
F
F
Dedicated clock output cycle-to-cycle jitter
F
F
Regular I/O period jitter
F
F
Regular I/O cycle-to-cycle jitter
F
F
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
Time required to reconfigure scan chains for PLLs
scanclk frequency
Period jitter for dedicated clock output in cascaded
PLLs (F
Period jitter for dedicated clock output in cascaded
PLLs (F
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
CCINT
 100 MHz
< 100 MHz
 100 MHz
< 100 MHz
 100 MHz
< 100 MHz
 100 MHz
< 100 MHz
through the decoupling capacitor and ferrite bead.
OUT
OUT
 100 MHz)
 100 MHz)
–12
(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
Parameter
(1), (2)
(Part 2 of 2)—Preliminary
Min
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
3.5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cyclone IV Device Handbook,
(7)
VCO
Max
42.5
300
300
650
650
±50
100
425
specification.
30
30
75
75
—
—
1
SCANCLK
cycles
MHz
Unit
mUI
mUI
mUI
mUI
mUI
Volume 3
ms
ps
ps
ps
ps
ps
ns
ps
1–25
CO