EP4CE15F17C9L Altera Corporation, EP4CE15F17C9L Datasheet - Page 27

• Manufacturer Part Number: EP4CE15F17C9L
• Description: IC CYCLONE IV FPGA 15K 256FBGA
• Manufacturer: Altera Corporation
• Series: CYCLONE® IV Er

Specifications of EP4CE15F17C9L

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 165
• Number Of Gates: -
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status: Contains lead
• Rohs Status: RoHS non-compliant

Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
November 2011 Altera Corporation
Periphery Performance
Table 1–29
Table 1–29. Active Configuration Mode Specifications for Cyclone IV Devices—Preliminary
Table 1–30
Table 1–30. JTAG Timing Parameters for Cyclone IV Devices
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the high-speed I/O
interface, external memory interface, and the PCI/PCI-X bus interface. I/Os using the
SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speeds. I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-,
1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency
with a 10 pF load.
Active Parallel (AP)
Active Serial (AS)
Note to
(1) AP configuration mode is only supported for Cyclone IV E devices.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes to
(1) For more information about JTAG waveforms, refer to
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V
(3) For EP4CGX22, EP4CGX30 (F324 and smaller package), EP4CGX110, and EP4CGX150 devices, the output time
Symbol
JCP
JCH
JCL
JPSU_TDI
JPSU_TMS
JPH
JPCO
JPZX
JPXZ
JSSU
JSH
JSCO
JSZX
JSXZ
LVTTL/LVCMOS and 1.5-V LVCMOS, the output time specification is 16 ns.
specification for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins is 16 ns. For 1.8-V LVTTL/LVCMOS
and 1.5-V LVCMOS, the output time specification is 18 ns.
Table
Programming Mode
Table
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time for TDI
JTAG port setup time for TMS
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
lists the active configuration mode specifications for Cyclone IV devices.
lists the JTAG timing parameters and values for Cyclone IV devices.
1–29:
1–30:
(1)
Parameter
(2),
(3)
DCLK Range
“JTAG Waveform”
20 to 40
20 to 40
(2),
(2),
(3)
(3)
(1)
—Preliminary
in
“Glossary” on page
Cyclone IV Device Handbook,
Min
40
19
19
10
—
—
—
10
—
—
—
1
3
5
MHz
MHz
Unit
Max
1–38.
—
—
—
—
—
—
15
15
15
—
—
25
25
25
Volume 3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1–27