EP4CE15F17C9L Altera Corporation, EP4CE15F17C9L Datasheet - Page 36

• Manufacturer Part Number: EP4CE15F17C9L
• Description: IC CYCLONE IV FPGA 15K 256FBGA
• Manufacturer: Altera Corporation
• Series: CYCLONE® IV Er

Specifications of EP4CE15F17C9L

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 165
• Number Of Gates: -
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status: Contains lead
• Rohs Status: RoHS non-compliant

1–36
Table 1–42. IOE Programmable Delay on Column Pins for Cyclone IV E 1.2 V Core Voltage Devices
Preliminary
Table 1–43. IOE Programmable Delay on Row Pins for Cyclone IV E 1.2 V Core Voltage Devices
Table 1–44. IOE Programmable Delay on Column Pins for Cyclone IV GX Devices
Cyclone IV Device Handbook,
Volume 3
Input delay from
dual-purpose clock pin
to fan-out destinations
Notes to
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Input delay from pin to
internal cells
Input delay from pin to
input register
Delay from output
register to output pin
Input delay from
dual-purpose clock pin
to fan-out destinations
Notes to
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Input delay from pin to
internal cells
Input delay from pin to
input register
Parameter
Parameter
Parameter
Table
Table
1–42:
1–43:
Table 1–44
devices.
Pad to global
clock
network
Pad to I/O
dataout to
core
Pad to I/O
input register
I/O output
register to
pad
Pad to global
clock
network
Pad to I/O
dataout to
core
Pad to I/O
input register
Affected
Affected
Affected
Paths
Paths
Paths
and
Table 1–45
Settings
Number
Number
Setting
Setting
Number
12
12
of
of
of
7
8
2
7
8
Offset
Offset
Offset
Min
Min
Min
list the IOE programmable delay for Cyclone IV GX
0
0
0
0
0
0
0
0.693 0.665 0.665 1.200 1.379 1.532 1.393 1.441
1.314 1.209 1.209 2.201 2.386 2.510 2.429 2.548
1.312 1.207 1.207 2.202 2.402 2.558 2.447 2.557
0.458 0.419 0.419 0.783 0.861 0.924 0.875 0.915
0.686 0.657 0.657 1.185 1.360 1.506 1.376 1.422
1.313
1.312
C6
C6
Fast Corner
C6
Fast Corner
Fast Corner
I7
I7
1.209
1.208
I7
A7
A7
2.184
2.200
C6
(1),
Max Offset
(2)
Max Offset
Max Offset
C6
C6
Chapter 1: Cyclone IV Device Datasheet
(Part 1 of 2)—Preliminary
2.336
2.399
Slow Corner
C7
November 2011 Altera Corporation
C7
C7
(1),
Slow Corner
Slow Corner
2.451
2.554
(2)
C8
(1),
—Preliminary
Switching Characteristics
C8
C8
(2)
(Part 2 of 2)—
2.387
2.446
I7
I7
I7
Unit
ns
ns
A7
A7
Unit
Unit
ns
ns
ns
ns
ns