EP4CE15F17C9L Altera Corporation, EP4CE15F17C9L Datasheet - Page 41

• Manufacturer Part Number: EP4CE15F17C9L
• Description: IC CYCLONE IV FPGA 15K 256FBGA
• Manufacturer: Altera Corporation
• Series: CYCLONE® IV Er

Specifications of EP4CE15F17C9L

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 165
• Number Of Gates: -
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status: Contains lead
• Rohs Status: RoHS non-compliant

Chapter 1: Cyclone IV Device Datasheet
Glossary
Table 1–46. Glossary (Part 4 of 5)
November 2011 Altera Corporation
Letter
U
T
t
Channel-to-
channel-skew
(TCCS)
t
t
t
t
t
t
Timing Unit
Interval (TUI)
t
t
t
t
t
Transmitter
Output
Waveform
t
t
C
cin
CO
cout
DUTY
FALL
H
INJITTER
OUTJITTER_DEDCLK
OUTJITTER_IO
pllcin
pllcout
RISE
SU
Term
—
High-speed receiver and transmitter input and output clock period.
High-speed I/O block: The timing difference between the fastest and slowest output edges,
including t
Delay from the clock pad to the I/O input register.
Delay from the clock pad to the I/O output.
Delay from the clock pad to the I/O output register.
High-speed I/O block: Duty cycle on high-speed transmitter output clock.
Signal high-to-low transition time (80–20%).
Input register hold time.
High-speed I/O block: The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t
Period jitter on the PLL clock input.
Period jitter on the dedicated clock output driven by a PLL.
Period jitter on the general purpose I/O driven by a PLL.
Delay from the PLL inclk pad to the I/O input register.
Delay from the PLL inclk pad to the I/O output register.
Transmitter output waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O
Standards:
Signal low-to-high transition time (20–80%).
Input register setup time.
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
CO
variation and clock skew. The clock is included in the TCCS measurement.
V os
V
OD
V
OD
Definitions
—
V
OD
Positive Channel (p) = V
Negative Channel (n) = V
Ground
0 V
p - n
Cyclone IV Device Handbook,
C
/w).
OH
OL
Volume 3
1–41