EP4CGX110CF23I7N Altera Corporation, EP4CGX110CF23I7N Datasheet - Page 38

• Manufacturer Part Number: EP4CGX110CF23I7N
• Description: IC CYCLONE IV FPGA 110K 484FBGA
• Manufacturer: Altera Corporation
• Series: CYCLONE® IV GXr

Specifications of EP4CGX110CF23I7N

• Number Of Logic Elements/cells: 109424
• Number Of Labs/clbs: 6839
• Total Ram Bits: 5621760
• Number Of I /o: 270
• Number Of Gates: -
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BGA
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

1–38
I/O Timing
Glossary
Table 1–46. Glossary (Part 1 of 5)
Cyclone IV Device Handbook,
Volume 3
Letter
D
G
H
A
B
C
E
F
I
f
GCLK
GCLK PLL
HSIODR
Input Waveforms
for the SSTL
Differential I/O
Standard
HSCLK
f
Term
—
—
—
—
—
Use the following methods to determine I/O timing:
■
■
The Excel-based I/O timing provides pin timing performance for each device density
and speed grade. The data is typically used prior to designing the FPGA to get a
timing budget estimation as part of the link timing analysis. The Quartus II timing
analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after place-and-route is complete.
The Excel-based I/O Timing spreadsheet is downloadable from
Literature
Table 1–46
the Excel-based I/O Timing
the Quartus II timing analyzer
V
High-speed I/O block: High-speed receiver/transmitter input and output clock frequency.
Input pin directly to Global Clock network.
Input pin to Global Clock network through the PLL.
High-speed I/O block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
SWING
website.
lists the glossary for this chapter.
Definitions
—
—
—
—
—
Chapter 1: Cyclone IV Device Datasheet
November 2011 Altera Corporation
Cyclone IV Devices
V
V
V
REF
IH
IL
I/O Timing