STM32F105V8 STMicroelectronics, STM32F105V8 Datasheet - Page 101

• Manufacturer Part Number: STM32F105V8
• Description: Mainstream Connectivity line, ARM Cortex-M3 MCU with 64 Kbytes Flash, 72 MHz CPU, CAN, USB 2.0 OTG
• Manufacturer: STMicroelectronics

Specifications of STM32F105V8

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Dma: 12-channel DMA controller
• Supported Peripherals: timers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter
• 10/100 Ethernet Mac With Dedicated Dma And Sram (4 Kbytes): IEEE1588 hardware support, MII/RMII available on all packages

STM32F105xx, STM32F107xx
Table 65.
14-Sep-2009
Date
Document revision history (continued)
Revision
4
Document status promoted from Preliminary data to full datasheet.
Number of DACs corrected in
STM32F107xx family versus STM32F103xx
Note 5
V
voltage.
Values added to
mode, code with data processing running from
Maximum current consumption in Run mode, code with data
processing running from RAM
consumption in Sleep mode, code running from Flash or
Typical I
current consumptions in Stop and Standby
Figure 10: Typical current consumption on VBAT with RTC on vs.
temperature at different VBAT values
Values modified in
mode, code with data processing running from Flash
Typical current consumption in Sleep mode, code running from Flash
or
f
characteristics.
C
characteristics
32.768
modified below
Conditions removed from
timings.
Standards modified in
page
Jitter maximum values added to
Table 28: PLL2 and PLL3
R
Condition added for V
characteristics. Note removed and R
Table 46: USB OTG FS DC electrical
Table 48: Ethernet DC electrical characteristics
Parameter values added to
Ethernet MAC signals for
Ethernet MAC signals for RMII
characteristics: Ethernet MAC signals for
C
characteristics. R
fADC = 14
Table 56: DAC characteristics
/non-buffered DAC
Table 64: Applicative current consumption in Run mode, code with
data processing running from Flash
Small text changes.
HSE_ext
Doc ID 15274 Rev 6
RERINT
L1
PU
ADC
RAM.
and C
and R
52, conditions modified in
and R
added in
kHz), notes modified and moved below the tables.
DD_VBAT
min modified in
and T
L2
PD
MHz.
AIN
replaced by C in
modified in
Coeff
and
Figure 16: Typical application with an 8 MHz
parameters modified in
Table 5: Pin
Table 13: Maximum current consumption in Run
value added in
AIN
Table 17: Typical current consumption in Run
added.
Table 23: LSE oscillator characteristics (fLSE =
added to
max values modified in
NF(NRST)
Section 5.3.10: EMC characteristics on
Table 20: High-speed external user clock
Table 36: I/O static
SMI,
Table 26: Low-power mode wakeup
characteristics.
Table 49: Dynamic characteristics:
definitions.
Table 12: Embedded internal reference
Changes
Table 22: HSE 3-25 MHz oscillator
Table 3: STM32F105xx and
modified.
parameter in
Table 50: Dynamic characteristics:
and
and
Table 31: EMS
Table 16: Typical and maximum
Table 27: PLL characteristics
Table 51: Dynamic
Table 15: Maximum current
PD
added.
characteristics.
added.
, R
Table 52: ADC
Figure 38: 12-bit buffered
MII.
PU
modes.
Table 39: NRST pin
family.
Table 53: RAIN max for
characteristics.
values added in
characteristics.
Flash,
added.
Revision history
and
Table 14:
RAM.
Note 1
Table 18:
crystal.
101/104
and