STM32F105V8 STMicroelectronics, STM32F105V8 Datasheet - Page 20

• Manufacturer Part Number: STM32F105V8
• Description: Mainstream Connectivity line, ARM Cortex-M3 MCU with 64 Kbytes Flash, 72 MHz CPU, CAN, USB 2.0 OTG
• Manufacturer: STMicroelectronics

Specifications of STM32F105V8

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Dma: 12-channel DMA controller
• Supported Peripherals: timers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter
• 10/100 Ethernet Mac With Dedicated Dma And Sram (4 Kbytes): IEEE1588 hardware support, MII/RMII available on all packages

Description
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Controller area network (CAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to
1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). The 256 bytes of SRAM which are allocated for each CAN (512 bytes in total)
are not shared with any other peripheral.
Universal serial bus on-the-go full-speed (USB OTG FS)
The STM32F105xx and STM32F107xx connectivity line devices embed a USB OTG full-
speed (12 Mb/s) device/host/OTG peripheral with integrated transceivers. The USB OTG FS
peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It
has software-configurable endpoint setting and supports suspend/resume. The USB OTG
full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL
connected to the HSE oscillator. The major features are:
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GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-
capable.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
I/Os on APB2 with up to 18 MHz toggling speed
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and group
addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive
FIFO are both 2 Kbytes, that is 4 Kbytes in total
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 with
the timestamp comparator connected to the TIM2 trigger input
Triggers interrupt when system time becomes greater than target time
1.25 KB of SRAM used exclusively by the endpoints (not shared with any other
peripheral)
4 bidirectional endpoints
HNP/SNP/IP inside (no need for any external resistor)
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
the SOF output can be used to synchronize the external audio DAC clock in
isochronous mode
in accordance with the USB 2.0 Specification, the supported transfer speeds are:
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in Host mode: full speed and low speed
in Device mode: full speed
Doc ID 15274 Rev 6
STM32F105xx, STM32F107xx