STM32F105V8 STMicroelectronics, STM32F105V8 Datasheet - Page 63

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STM32F105V8

Manufacturer Part Number
STM32F105V8
Description
Mainstream Connectivity line, ARM Cortex-M3 MCU with 64 Kbytes Flash, 72 MHz CPU, CAN, USB 2.0 OTG
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F105V8

Core
ARM 32-bit Cortex™-M3 CPU
Conversion Range
0 to 3.6 V
Dma
12-channel DMA controller
Supported Peripherals
timers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs
Systick Timer
a 24-bit downcounter
10/100 Ethernet Mac With Dedicated Dma And Sram (4 Kbytes)
IEEE1588 hardware support, MII/RMII available on all packages

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0
STM32F105xx, STM32F107xx
5.3.16
Communications interfaces
I
Unless otherwise specified, the parameters given in
performed under the ambient temperature, f
conditions summarized in
The STM32F105xx and STM32F107xx I
standard I
SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
The I
injection characteristics
(SDA and SCL) .
Table 41.
1. Guaranteed by design, not tested in production.
2. f
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
2
t
C interface characteristics
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
su(SDA)
t
t
su(STO)
achieve the fast mode I
maximum clock 400 kHz.
period of SCL signal.
undefined region of the falling edge of SCL.
t
t
t
su(STA)
h(SDA)
PCLK1
r(SDA)
h(STA)
r(SCL)
f(SDA)
f(SCL)
C
2
C characteristics are described in
b
must be at least 2 MHz to achieve standard mode I
2
C communication protocol with the following restrictions: the I/O pins SDA and
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
Stop condition setup time
Stop to Start condition time
(bus free)
Capacitive load for each bus
line
I
2
C characteristics
Parameter
2
C frequencies and it must be a mulitple of 10 MHz in order to reach I
for more details on the input/output alternate function characteristics
Table
Doc ID 15274 Rev 6
9.
DD
Standard mode I
2
Table
is disabled, but is still present.
C interface meets the requirements of the
Min
250
0
4.7
4.0
4.0
4.7
4.0
4.7
PCLK1
(3)
41. Refer also to
2
frequency and V
C frequencies. It must be at least 4 MHz to
Table 41
1000
Max
300
400
2
C
(1)
are derived from tests
20 + 0.1C
Fast mode I
Section 5.3.12: I/O current
Electrical characteristics
Min
100
0
1.3
0.6
0.6
0.6
0.6
1.3
(4)
DD
supply voltage
b
2
C
900
Max
300
300
400
(1)(2)
2
C fast mode
(3)
63/104
Unit
μs
μs
pF
µs
ns
µs

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