STM32F105VC STMicroelectronics, STM32F105VC Datasheet - Page 59

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STM32F105VC

Manufacturer Part Number
STM32F105VC
Description
Mainstream Connectivity line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, CAN, USB 2.0 OTG
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F105VC

Core
ARM 32-bit Cortex™-M3 CPU
Conversion Range
0 to 3.6 V
Dma
12-channel DMA controller
Supported Peripherals
timers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs
Systick Timer
a 24-bit downcounter
10/100 Ethernet Mac With Dedicated Dma And Sram (4 Kbytes)
IEEE1588 hardware support, MII/RMII available on all packages

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STM32F105xx, STM32F107xx
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/-20 mA (with a relaxed V
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in
Output voltage levels
Unless otherwise specified, the parameters given in
performed under ambient temperature and V
Table
Table 37.
1. The I
2. The I
3. Based on characterization data, not tested in production.
V
V
Symbol
V
V
V
V
V
V
OH
OH
OL
OL
OH
OL
OH
and the sum of I
Table 7
OL
(1)(3)
(1)(3)
(2)(3)
(2)(3)
The sum of the currents sourced by all the I/Os on V
consumption of the MCU sourced on V
I
The sum of the currents sunk by all the I/Os on V
consumption of the MCU sunk on V
I
VDD
VSS
(1)
(2)
(1)
(2)
9. All I/Os are CMOS and TTL compliant.
IO
IO
current sunk by the device must always respect the absolute maximum rating specified in
current sourced by the device must always respect the absolute maximum rating specified in
(see
and the sum of I
(see
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Output voltage characteristics
Table
Table
IO
(I/O ports and control pins) must not exceed I
7).
7).
IO
Parameter
(I/O ports and control pins) must not exceed I
Doc ID 15274 Rev 6
OL
SS
/V
DD,
cannot exceed the absolute maximum rating
OH
DD
cannot exceed the absolute maximum rating
).
supply voltage conditions summarized in
2.7 V < V
2.7 V < V
2.7 V < V
2 V < V
Section
I
Conditions
I
IO
I
CMOS port
I
Table 37
IO
IO
IO
TTL port
SS
= +20 mA
= +8 mA
= +6 mA
VSS
=+ 8mA
DD
DD
DD
DD
plus the maximum Run
DD,
.
5.2:
< 2.7 V
< 3.6 V
< 3.6 V
< 3.6 V
plus the maximum Run
VDD
are derived from tests
.
Electrical characteristics
V
V
V
DD
DD
DD
Min
2.4
–0.4
–1.3
–0.4
Max
0.4
0.4
1.3
0.4
Table 7
59/104
Unit
V
V
V
V

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