STM32F105VC STMicroelectronics, STM32F105VC Datasheet - Page 66

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STM32F105VC

Manufacturer Part Number
STM32F105VC
Description
Mainstream Connectivity line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, CAN, USB 2.0 OTG
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F105VC

Core
ARM 32-bit Cortex™-M3 CPU
Conversion Range
0 to 3.6 V
Dma
12-channel DMA controller
Supported Peripherals
timers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs
Systick Timer
a 24-bit downcounter
10/100 Ethernet Mac With Dedicated Dma And Sram (4 Kbytes)
IEEE1588 hardware support, MII/RMII available on all packages

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Electrical characteristics
Figure 25. SPI timing diagram - slave mode and CPHA = 0
Figure 26. SPI timing diagram - slave mode and CPHA = 1
1. Measurement points are done at CMOS levels: 0.3V
66/104
OUT P UT
OUT P UT
NSS input
NSS input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
I NPUT
I NPUT
MISO
MISO
MOSI
MOSI
t a(SO)
t SU(NSS)
t a(SO)
t su(SI)
t w(SCKH)
t w(SCKL)
t w(SCKH)
t w(SCKL)
t su(SI)
t SU(NSS)
MS B O UT
t v(SO)
M SB IN
M SB IN
t h(SI)
MS B O UT
t c(SCK)
t v(SO)
t h(SI)
Doc ID 15274 Rev 6
DD
t c(SCK)
and 0.7V
BI T6 OUT
B I T1 IN
t h(SO)
DD
.
B I T1 IN
BI T6 OUT
(1)
t h(SO)
LSB IN
STM32F105xx, STM32F107xx
t r(SCK)
t f(SCK)
LSB OUT
t r(SCK)
t f(SCK)
t h(NSS)
LSB IN
t h(NSS)
LSB OUT
t dis(SO)
t dis(SO)
ai14134c
ai14135

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