STM32F105VC STMicroelectronics, STM32F105VC Datasheet - Page 68

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STM32F105VC

Manufacturer Part Number
STM32F105VC
Description
Mainstream Connectivity line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, CAN, USB 2.0 OTG
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F105VC

Core
ARM 32-bit Cortex™-M3 CPU
Conversion Range
0 to 3.6 V
Dma
12-channel DMA controller
Supported Peripherals
timers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs
Systick Timer
a 24-bit downcounter
10/100 Ethernet Mac With Dedicated Dma And Sram (4 Kbytes)
IEEE1588 hardware support, MII/RMII available on all packages

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Electrical characteristics
Table 44.
1. Based on design simulation and/or characterization results, not tested in production.
68/104
f
1/t
t
t
t
t
t
t
t
t
DuCy(SCK)
t
t
t
t
t
t
t
t
CK
r(CK)
f(CK)
w(CKH)
w(CKL)
v(WS)
h(WS)
su(WS)
h(WS)
su(SD_MR)
su(SD_SR)
h(SD_MR)
h(SD_SR)
v(SD_ST)
h(SD_ST)
v(SD_MT)
h(SD_MT)
c(CK)
Symbol
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)(3)
(1)
(1)
(1)
(1)
(1)
(1)
I
2
S characteristics
I
I
I
I
WS valid time
WS hold time
WS setup time
WS hold time
I2S slave input clock duty
cycle
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
2
2
2
2
S clock frequency
S clock rise and fall time
S clock high time
S clock low time
Parameter
Master data: 16 bits, audio
freq = 48 K
Slave
capacitive load C
Master f
audio freq = 48 K
Master mode
Master mode
Slave mode
Slave mode
Slave mode
Master receiver
Slave receiver
Master receiver
Slave receiver
Slave transmitter
(after enable edge)
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
Master transmitter
(after enable edge)
Doc ID 15274 Rev 6
Conditions
PCLK
= 16 MHz,
L
= 50 pF
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
1.52
Min
333
317
30
10
23
33
29
27
11
0
3
0
0
4
9
0
8
3
8
2
4
2
4
4
STM32F105xx, STM32F107xx
Max
1.54
320
336
6.5
70
8
5
2
MHz
Unit
ns
ns
%

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