STM32F105VC STMicroelectronics, STM32F105VC Datasheet - Page 99

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STM32F105VC

Manufacturer Part Number
STM32F105VC
Description
Mainstream Connectivity line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, CAN, USB 2.0 OTG
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F105VC

Core
ARM 32-bit Cortex™-M3 CPU
Conversion Range
0 to 3.6 V
Dma
12-channel DMA controller
Supported Peripherals
timers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs
Systick Timer
a 24-bit downcounter
10/100 Ethernet Mac With Dedicated Dma And Sram (4 Kbytes)
IEEE1588 hardware support, MII/RMII available on all packages

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STM32F105xx, STM32F107xx
Revision history
Table 65.
18-Dec-2008
20-Feb-2009
Date
Document revision history
Revision
1
2
Initial release.
I/O information clarified
STM32F107xxx connectivity line BGA100 ballout top view
Section 2.3.8: Boot modes
PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default
column to Remap column, plus small additional changes in
Pin
Consumption values modified in
characteristics.
Note modified in
mode, code with data processing running from Flash
Maximum current consumption in Sleep mode, code running from
Flash or
Table 20: High-speed external user clock characteristics
Table 21: Low-speed external user clock characteristics
Table 27: PLL characteristics
characteristics
Doc ID 15274 Rev 6
definitions.
RAM.
added.
Table 13: Maximum current consumption in Run
on page
updated.
modified and
Changes
Section 5.3.5: Supply current
1.
Figure 4: STM32F105xxx and
Table 28: PLL2 and PLL3
Revision history
and
modified.
and
Table 15:
corrected.
Table 5:
99/104

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